Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-12-17
2002-03-26
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S001000, C710S022000, C710S120000, C709S208000, C712S033000, C712S034000, C712S035000, C712S036000, C712S200000, C712S225000
Reexamination Certificate
active
06363444
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The invention is related to the field of processing systems, and more particularly to the transfer of data among different processing elements within a processing system.
Processing systems require communication mechanisms among elements. An example of a specialized processing system having need for a communication mechanism is a network interface card (NIC) of the type used in host systems such as personal computers and workstations. NICs are generally plug-in circuit cards having an interface to an I/O bus used in the host system, along with an interface to a physical network medium. In a NIC, it is common to employ random access memory (RAM) as temporary buffer storage for packets that have been received from the network or that are to be transmitted on the network. Along with the buffer RAM, the NIC contains a significant amount of complex logic for implementing the respective interfaces to the host I/O bus and the network, and to move data along respective datapaths between the I/O bus and the buffer RAM, and between the network and the buffer RAM. This complex logic is often embedded in a small number (perhaps only one) of so-called application-specific integrated circuits (ASICs). Some NICs may include a microprocessor having access to the buffer RAM through the ASIC logic, in order to provide desired functionality not readily implemented in hardware alone. Whether such a microprocessor is included or not, the ASIC logic can be viewed as a “master processor” with respect to the buffer RAM, because all transfers of data to and from the buffer RAM are controlled by the ASIC logic.
While it is necessary to provide communication between a master processor and memory, it may also be desirable in NICs or other systems to provide support for some type of co-processor. A NIC, for example, may be designed to support an optional encryption engine, which may consist of one or more integrated circuits. The encryption engine is used to encrypt outgoing packets and to decrypt incoming packets. To support such a co-processor, communication paths are needed between the co-processor and the other system elements, so that packet data can be rapidly transferred into and out of the co-processor. It can be desirable, therefore, to incorporate an interface to a co-processor in ASIC logic or a similar master processor.
It is generally known that the number of input/output pins used on an integrated circuit (IC) can affect the cost of the IC. Costs associated with testing, packaging, and decreased manufacturing yield, for example, are directly affected by the number of I/O pins on a packaged device. Additionally, ICs having a number of separate interfaces are generally more complex and difficult to design and verify than ICs having a simpler interface structures. It is generally desirable to minimize such costs and complexities. Accordingly, there is a need in the art for a co-processor interface that does not require a large number of additional pins on a master processor.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a processing system is disclosed in which an optional co-processor is supported without requiring a separate interface on a master processor. High system performance is achieved, while device cost and complexity are reduced by keeping pin counts relatively low.
In the processing system, a master processor, such as a complex ASIC as discussed above, is coupled to a memory via a memory data bus. The master processor supplies an address and control signals to the memory, enabling the master processor to control the reading and writing of the memory at addressed locations. Thus data can be transferred between the master processor and the memory. Additionally, a slave processor, such as an encryption engine in one embodiment, has a data input/output bus connected directly to the memory data bus. The master processor supplies control signals to the slave processor to control the reading and writing of data to/from the slave processor via the memory data bus.
The master processor effects data transfers directly between the memory and the slave processor over the memory data bus. To transfer data from the memory to the slave processor, the master processor generates a series of memory addresses to read data from addressed locations of the memory onto the data bus. As the data word from each memory location appears on the data bus, the master processor writes the data word into the slave processor. To transfer data from the slave processor to the memory, the master processor reads a series of data from the slave processor onto the data bus, generates a series of memory addresses on the address output as the data are being read from the slave processor, and as each data word from the slave processor appears on the data bus, writes the data word into the addressed location of the memory. Thus, data flows directly between the memory and the slave processor without passing through the master processor. The only additional pins required by the master processor are the pins for the control signals to the slave processor.
Other aspects, features and advantages of the present invention will be apparent from the detailed description below.
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Connery Glenn
Platko John J.
Reissfelder Robert
3COM Corporation
Lee Thomas C.
Nguyen Tanh
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