Skip based control logic for first in first out buffer

Details Skip based control logic for first in first out buffer Skip based control logic for first in first out buffer

2008-09-30

2011-10-18

Hafiz, Tatiq (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S005000, C710S031000, C710S033000

Reexamination Certificate

active

08041856

ABSTRACT:
A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.

REFERENCES:
patent: 7362771 (2008-04-01), Lo et al.
patent: 2002/0057510 (2002-05-01), Hoskins et al.
patent: 2007/0002991 (2007-01-01), Thompson et al.
Chu, Pong P., FPGA prototyping by VHDL examples: Xilinx Spartan-3 version, 2008, John Wiley and Sons, pp. 100-108 [Online, accessed Nov. 5, 2010, available from Google Books].

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