Skew-reduction circuit and semiconductor device

Details Skew-reduction circuit and semiconductor device Skew-reduction circuit and semiconductor device

1997-10-30

1999-08-10

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

G06F 104, H03K 5135

Patent

active

059352574

ABSTRACT:
A circuit for reducing skews includes a clock switching unit, receiving a clock signal, which outputs the clock signal in a first mode, and outputs a delayed clock signal obtained by delaying the clock signal in a second mode. The circuit further includes a skew reducing unit, receiving an input signal, which adjusts a phase of the input signal based on the clock signal from the clock switching unit in the first mode, and latches the input signal having an adjusted phase by using the delayed clock signal from the clock switching unit in the second mode.

REFERENCES:
patent: 5204559 (1993-04-01), Deyhimy et al.
patent: 5369640 (1994-11-01), Watson et al.
patent: 5628000 (1997-05-01), Kashiyama et al.

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