Skew pointer generation

Details Skew pointer generation Skew pointer generation

1999-03-22

2002-04-02

Heckler, Thomas M. (Department: 2709)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

Reexamination Certificate

active

06367027

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to data transfer devices and more particularly, to a data transfer device which reduces delay between output data and a clock cycle.
2. Description of the Related Art
In digital devices, such as memory devices, data transfer to and from first in/first out devices (FIFOs) is controlled using input/output pointers. FIFOs are memory devices which output data in the same order as entered at the input. A relationship between the pointers which control the FIFO and a clock need to be well defined. It is particularly desirable for high frequency designs to maintain a substantially constant delay between the pointers and the clock.
Referring to
FIG. 1
, a conventional 1 out-of-8 decoder
10
is shown. Using binary counters for input and/or output pointer generation employs decoder
10
to output a bit representing a number input from binary counters. To decode a “0” inputs are Q
0
=0, Q
1
=0 and Q
2
=0. The pointer output for a FIFO-latch <
0
> is “0” all others are one. Decoder must invert all “0”s to “1”s and NAND them using invertors
12
and NAND gate
14
, respectively to output decoder FIFO latch <
0
>. For decoding a “7” the binary counter signals to decoder are Q
0
=1, Q
1
=1 and Q
2
=1. The pointer output for a FIFO-latch <
7
> is “0” all others are one. Decoder uses all “1”s without using invertors. NAND gate
16
, NANDs the inputs at decoder for FIFO latch <
7
> to provide an output of “1”. Other pointers for FIFO latches <
1
> to <
6
>, have different inverter combinations in decoder to decode the binary counter inputs. timing diagram shows a clock pulse (CLK) as compared to the pointers for FIFO latches <
0
> and <
7
>. The decoding of a “
0
” includes invertors
12
which introduce additional delay between the pointer from FIFO latch <
0
> and CLK. The delay is represented by td+&dgr;. The decoding of a “
7
” does not include invertors. The delay is represented by td. The additional delay of &dgr; is typically in the order of hundreds of pico seconds. This uncertainty in the pointer signals with respect to CLK is not desired.
Referring to
FIG. 3
, another timing diagram is shown for a prior art FIFO illustratively depicts a clock signal CLK and pointer signals PTR <
0
>, PTR <
1
>, and PTR <
7
>. Pointer signals each have a delay &dgr; ciated therewith and indicated in the timing diagram. As is apparent from
FIG. 3
, &dgr;
0
≠&dgr;
1
≠ . . . &dgr;
7
. This inequality between delay leads to differences in time for data output Dout as indicated by &tgr;
0
, &tgr;
1
and &tgr;
7
. &tgr;
0
≠&tgr;
1
≠ . . . ≠&tgr;
7
which results in a skew problem.
Therefore, a need exists for pointer generation which includes pointers having a substantially same delay with respect to a clock. A further need exists for a method of providing FIFO memory with pointers with the substantially same delay with respect to the clock.
SUMMARY OF THE INVENTION
A pointer generation circuit, in accordance with the invention, includes a clock for providing a clock cycle, and a shift register with a plurality of latches for storing data bits. A first latch receives a flag bit upon a first clock cycle of the clock. A switch transfers the flag bit to the shift register on the first clock cycle. The switch connects a last latch to the first latch after the flag bit is transferred to the shift register. The flag bit is transferred to a next latch, wherein the next latch for the last latch is the first latch, at each consecutive clock cycle thereby generating pointer signals in accordance with the clock cycle and the data bits stored in the latches. The flag bit is transferred to a next latch, wherein the next latch for the last latch is the first latch, at each consecutive clock cycle thereby generating pointer signals in accordance with the clock cycle and the data bits stored in the latches.
Another pointer generation circuit in accordance with the invention includes a clock for providing a clock cycle. A shift register includes a plurality of latches for storing data bits. A first latch receives a flag bit upon a first clock cycle of the clock. A switch transfers the flag bit to the shift register on the first clock cycle. The switch connects a last latch to the first latch after the flag bit is transferred to the shift register. The flag bit being transferred to a next latch, wherein the next latch for the last latch is the first latch, at each consecutive clock cycle thereby generating output signals in accordance with the clock cycle and the data bits stored in the latches. A pulse generation circuit is included for receiving the output signals and generating a pointer signal having a predetermined pulse width.
In alternate embodiments, the flag bit is preferably a digital “1” and the latches other than the latch including the flag bit are digital“0”s. The shift register may include eight latches. The latches of the shift register may output to a first in/first out (FIFO) memory device. Each clock cycle may include a first signal edge and the latches preferably output a pointer signal such that a time delay for the pointer signal from each latch is substantially equal relative to the first signal edge of a corresponding clock cycle. The circuit may be included on an integrated circuit chip.
A method for pointer generation for first in/first out memories includes the steps of providing a pointer generation circuit including a clock for providing a clock cycle, a shift register including a plurality of latches for storing data bits, a first latch for receiving a flag bit upon a first clock cycle of the clock, initializing the latches to a data bit value, transferring the flag bit to the first latch, connecting the last latch to the first latch, transferring the flag bit to a next latch, wherein the next latch for the last latch is the first latch, corresponding to each clock cycle and generating pointer signals in accordance with the clock cycle by outputting the data bits stored in the latches.
In other methods, the flag bit is preferably a digital “1” and the data bit value is a digital “0”. The shift register may include eight latches. The step of generating pointer signals may include the step of generating pointer signals in accordance with the clock cycle by outputting the data bits stored in the latches to a pulse generating circuit. The method may further include the step of generating pulses of a predetermined pulse width by the pulse generating circuit. Each clock cycle may include a first signal edge, and the method may further include the step of outputting a pointer signal from the latches such that a time delay for the pointer signal from each latch is substantially equal relative to the first signal edge of a corresponding clock cycle. The pointer generation circuit preferably includes a switch and the method may further include the steps of transferring the flag bit to the shift register on the first clock cycle through the switch, connecting a last latch to the first latch through the switch after the flag bit is transferred to the shift register.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 3893088 (1975-07-01), Bell
patent: 4014550 (1977-03-01), Wilcox
patent: 4395764 (1983-07-01), Matsue
patent: 5689689 (1997-11-01), Meyers et al.
patent: 6134155 (2000-10-01), Wen
patent: 0 286 356 (1988-10-01), None

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