Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
Reexamination Certificate
1999-04-05
2001-12-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Skew detection correction
C714S731000, C714S735000
Reexamination Certificate
active
06327678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a skew adjusting method in an IC testing apparatus for testing various kinds of semiconductor integrated circuits (each referred to as IC, hereinafter) and determining whether they are defectless (pass) or defective (failure), and more particularly, to an adjusting method for conforming the timing at which a test pattern signal is applied to each of terminals of an IC under test and the timing at which a response output signal outputted from the IC under test is fetched or read out, to a predetermined set value for each terminal, called skew adjusting method in this field (hereinafter referred to skew adjusting method), and a pseudo device which is used in this skew adjusting method.
2. Description of the Related Art
In an IC testing apparatus for testing ICs such as, for example, memories, it is conventional that an adjustment in which the timing for applying a test pattern signal to each of input terminals (a data input terminal and an address input terminal) of an IC under test and the timing for reading out a response output signal from an output terminal of the IC under test or an
110
terminal of the IC under test in its output mode are conformed to a predetermined set value for each terminal, is periodically conducted. This adjustment is commonly called skew adjustment In this technical field.
In a test head of the IC testing apparatus, there is housed a printed board, called a pin card in this field, which contains, for example, a driver for applying a test pattern signal to an IC under test through an IC socket mounted on top of the test head, and a comparator for comparing a response output signal fetched through the IC socket from the IC under test with an expected value signal, and the like. The printed board will hereinafter be referred to as pin card. Usually there are housed a plurality of pin cards the number of which corresponds to the number of terminals (pins) of an IC under test.
FIG. 3
schematically depicts, by way of example, the circuit configuration of such a pin card. Since pin cards
11
A,
11
B,
11
C, . . . ,
11
N have the same circuit configuration with one another, there is shown in
FIG. 3
the circuit configuration of only the pin card
11
A. The pin cards
11
A through
11
N are each designed so that when they are placed in the test head at predetermined positions thereof, the output terminals of the drivers are electrically connected to an IC socket and one input terminal of each of the comparators is electrically connected to the IC socket.
As depicted in
FIG. 3
, the pin card
11
A comprises a waveform generator FF, a driver DR for amplifying a test pattern signal generated by the waveform generator FF and applying the amplified test pattern signal to an IC under test via a terminal P
1
of an IC socket
10
, and a voltage comparator CP for comparing a response output signal from the IC under test with an expected value signal.
The IC socket
10
, to which the IC under test (not shown) is to be electrically connected, has terminals (pins) P
1
, P
2
, P
3
, . . . , P
N
corresponding in number to terminals (pins) of the IC under test to which the terminals P
1
to P
N
are connected. To the terminates P
1
to P
N
are each connected the output terminal of the driver DR and one input terminal of the voltage comparator CP of the corresponding one of the pin cards
11
A to
11
N.
The waveform generator FF is formed, in this example, by an S-R flip-flop provided with a set terminal S and a reset terminal R. When supplied at its set terminal S with a set input signal PSET (shown in
FIG. 4B
) from an input terminal SET of the pin card
11
A via a variable delay circuit DRY
1
, the S-R flipflop FF generates a driving signal V
DR
that goes to a logical H (high level) as depicted in FIG.
4
D.
On the other hand, when supplied at its reset terminal R with a reset input signal P
RESET
(shown in
FIG. 4C
) from an input terminal RESET of the pin card
11
A via a variable delay circuit DRY
2
, the S-R flip-flop FF makes the driving signal VDR L-logic (lowlevel) as depicted in FIG.
4
D.
In this way, the S-R flip-flop FF generates the driving signal V
DR
in response to the application thereto of the set input signal P
SET
and the reset input signal P
RESET
. The driving signal VDR is amplified by the driver DR, from which it is fed as a test pattern signal via the corresponding terminal P
1
of the IC socket
10
to the corresponding input terminal (an address input terminal and a dedicated input terminal, or an Input terminal of a combination I/O terminal in the input mode) of the IC under test. Needless to say, the waveform generator FF is not limited specifically to the S-R flipflop but may also be formed by other devices or circuits as long as they serve the intended purpose.
The set input signal P
SET
and the reset input signal P
RESET
are delayed for &tgr;
1
and &tgr;
2
, respectively, relative to the generation timing of period pulses P
RET
that define the test period T
TES
as shown in
FIG. 4A
, and then they are input into the set input terminal SET and the reset input terminal RESET of each of the pin cards
11
A to
11
N. The delay times r and &tgr;
2
are determined by the condition for the generation of the test pattern.
Now, assuming that the delay times of the set and reset input signals PSET and PRESET fed to the input terminals SET and RESET of all the pin cards
11
A to
11
N are &tgr;
1
and &tgr;
2
depicted in
FIGS. 4B and 4C
, respectively, test pattern signals ought to be applied in the same phase (at the same timing) to the respective terminals P
1
to P
N
of the IC socket
10
.
In practice, however, due to variations in the line lengths between the pin cards
11
A to
11
N and the corresponding terminals P
1
to P
N
of the IC socket
10
, or by some other cause, the signal propagation delay time T
pd
shown in
FIG. 3
varies accordingly, resulting in variations In the timing of arrival of the driving signals VDR at the terminals P
1
to PN of the IC socket
10
. To accommodate the variations in this timing and hence ensure in-phase application of the test pattern signals to the IC socket, the pin cards
11
A to
11
N are each provided with the aforementioned variable delay circuits DRY
1
and DRY
2
. By controlling the delay times of the variable delay circuits DRY
1
and DRY
2
, the phases of the driving signals V
DR
to be supplied to all the terminals P
1
to P
N
of the IC socket
10
are adjusted into coincidence with the phases of the set and reset input signals P
SET
and P
RESET
fed to the input terminals SET and REST of the pin cards
11
A to
11
N. This is the aforementioned skew adjustment.
In addition, when there are variations in the propagation delay time T
pd
between the pin cards
11
A to
11
N and the corresponding terminals of the IC socket
10
, variations also result in the propagation time for the response output signal read out of the IC under test to reach the voltage comparator CP of the corresponding one of the pin cards
11
A to
11
N. To accommodate the variations, there is placed l variable delay circuit DRY
3
in a path over which a strobe pulse P
STRB
is supplied to the voltage comparator CP via a strobe input terminal STRB of each pin card, by which skew adjustments are made on the voltage comparator CP side as well.
Next, a description will be given of conventional skew adjusting methods on the driver DR side and on the voltage comparator CP side.
Conventionally, to make skew adjustments on the driver DR side, a standard voltage comparator STDCP is provided as standard phase detecting means as shown in
FIG. 3
; output terminals of the pin cards
11
A to
11
N are selectively connected via a relay matrix RMAX to the standard voltage comparator STDCP in a sequential order to make the skew adjustment for each of the pin cards
11
A to
11
N. The skew adjustment for the pin card
11
A will be described below by way of example.
The standard voltage comparator STDCP is provided with first and seco
Advantest Corporation
De'cady Albert
Gallagher & Lathrop
Lathrop, Esq. David N.
Torres Joseph D.
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