Skew adjusting circuit and semiconductor integrated circuit

Details Skew adjusting circuit and semiconductor integrated circuit Skew adjusting circuit and semiconductor integrated circuit

2005-09-13

2005-09-13

Chase, Shelly A (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

Reexamination Certificate

active

06944801

ABSTRACT:
An output signal of a flip flop at an output stage is supplied to delay gates connected in series thereto. A selector selects the output signal of the flip flop at the output stage or an output signal of one of the delay gates and supplies the selected signal to an external device. A signal to be selected by the selector depends on the value of data stored in a selector value setting register. When a skew adjustment is performed, the output signal of the flip flop at the output stage is held in a write data holding register. The signal supplied to the external device is held in a read data buffer through an input/output register of the external device. Until the value of the signal stored in the write data holding register matches the value of the signal held in the read data buffer, the value of the data stored in the selector value setting register is varied.

REFERENCES:
patent: 6032282 (2000-02-01), Masuda et al.
patent: 6335647 (2002-01-01), Nagano
patent: 6570428 (2003-05-01), Liao et al.
patent: 1-149154 (1989-06-01), None
patent: 5-45418 (1993-02-01), None
patent: H10-164037 (1998-06-01), None
patent: H10-171549 (1998-06-01), None
patent: H11-219323 (1999-08-01), None
patent: 11-316619 (1999-11-01), None
patent: 2000-250651 (2000-09-01), None

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