Skew adjusting circuit and method for parallel signals

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate

Reexamination Certificate

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C375S371000, C375S355000

Reexamination Certificate

active

07441139

ABSTRACT:
The skew adjusting circuit for parallel signals includes: a deskew signal generating circuit which generates a deskew signal by performing a predetermined logical operation and transmits the deskew signal to a receiving circuit; a skew detecting circuit which detects the skew by obtaining correlation between the deskew signal and the data signal and then obtaining an average value of the correlation; and a delay amount adjusting circuit which adjusts the skew by controlling the amount of delay of the data signal in accordance with the average value obtained by the skew detecting circuit. As a result, it is possible to reduce power consumption and circuit size, while suppressing the number of logic processing circuits to be added for skew adjustment, when parallel signals are transmitted in circuits which needs high-speed characteristic.

REFERENCES:
patent: 6480021 (2002-11-01), Deas et al.
patent: 7054401 (2006-05-01), Kada et al.
patent: 7123660 (2006-10-01), Haq et al.
patent: 2002/0009169 (2002-01-01), Watanabe
patent: 10-164037 (1998-06-01), None
patent: 11074945 (1999-03-01), None
patent: 2004-531117 (2004-10-01), None
patent: WO 02/069552 (2002-09-01), None

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