Size-based interleaving in a packet-based link

Details Size-based interleaving in a packet-based link Size-based interleaving in a packet-based link

2005-06-29

2008-12-02

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S100000, C711S154000

Reexamination Certificate

active

07461218

ABSTRACT:
A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.

REFERENCES:
patent: 4451880 (1984-05-01), Johnson et al.
patent: 6009488 (1999-12-01), Kavipurapu
PCI-SIG, “PCI Express™ Base Specification Revision 1.0a,” pp. 1-426, Apr. 15, 2003.

Affiliated with

Also associated with

Rating

Size-based interleaving in a packet-based link does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Size-based interleaving in a packet-based link, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Size-based interleaving in a packet-based link will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4023584