Six-transistor (6T) static random access memory (SRAM) with...

Details Six-transistor (6T) static random access memory (SRAM) with... Six-transistor (6T) static random access memory (SRAM) with...

2007-02-13

2007-02-13

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189050, C365S189090, C365S189110

Reexamination Certificate

active

10883609

ABSTRACT:
In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

REFERENCES:
patent: 6166985 (2000-12-01), McDaniel et al.
patent: 2003/0090927 (2003-05-01), Zhang et al.
patent: 2004/0019703 (2004-01-01), Burton
patent: 2005/0021606 (2005-01-01), Davies et al.
patent: 2005/0047196 (2005-03-01), Bhavnagarwala et al.
patent: 2005/0213370 (2005-09-01), Khellah et al.
patent: 2005/0246568 (2005-11-01), Davies

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