Six-input look-up table and associated memory control...

Details Six-input look-up table and associated memory control... Six-input look-up table and associated memory control...

2006-07-11

2006-07-11

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000, C326S039000, C326S040000, C326S041000, C326S046000, C326S047000, C706S050000, C716S030000

Reexamination Certificate

active

07075332

ABSTRACT:
A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. Sixty-four write control circuits are coupled to the 64 memory cells. A first write address decoder receives a first subset of the six input signals, and in response, provides a first set of write select signals to the 64 write control circuits. A second write address decoder receives a second subset of the six input signals and a write clock signal, and in response, provides a plurality of decoded write clock signals to the sixty-four write control circuits. A write data value, which is applied to each of the write control circuits, is written to one of the memory cells in a synchronous manner with respect to the write clock signal in response to the first set of write select signals and the decoded write clock signals.

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