SISO decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

active

07415659

ABSTRACT:
The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratio's in a single operation, as opposed to the two pass traditionally associated with the Tanner Graph's. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISO's. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

REFERENCES:
patent: 6526538 (2003-02-01), Hewitt
patent: 7093179 (2006-08-01), Shea
William Ryan, “An Introduction to Low-Density Parity-Check Codes”, tutorial, Apr. 2001, USA.
Lin-Nan Lee, “Description of HNS FEC Proposqal”, Hughes Network Systems publication, Dec. 16, 2002, USA.

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