Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1999-05-21
2001-07-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S121000, C438S175000, C438S430000, C438S581000, C257S190000, C257S194000, C257S283000, C257S280000
Reexamination Certificate
active
06258639
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to field effect transistors.
BACKGROUND ART
A high electron mobility field-effect transistor (HEMT), or modulation-doped field effect transistor (MODFET), is an extremely fast transistor device that is used in high-speed monolithic microwave integrated circuits (MMICs). Applications for HEMTs include wireless millimeter-wave communications, fiber-radio personal communication systems, automobile collision-avoidance radar, and optical fiber and low-noise direct broadcast satellite (DBS) communications receivers.
A typical HEMT includes a Schottky barrier layer overlying a donor layer, both of which are typically formed of a wide band-gap semiconductor such as an aluminum-containing material. Exposure of the Schottky barrier layer, the semiconductor surface, or the donor layer, to impurities during the fabrication process or during the normal operation of the HEMT can result in the degradation of the semiconductor surface of the Schottky barrier and/or the underlying donor layer. This adversely affects the performance and the reliability of the HEMT.
It should be noted that the term “degradation” is used herein and applies to oxidation, fluorine passivation, and other forms of deterioration due to the presence of impurities.
Various solutions to these degradation problems have been proposed. Most of the solutions typically involve the use of one or more thin epitaxial layers of an aluminum-free semiconductor as “stop layers” to prevent degradation of the Schottky barrier layer and/or the underlying donor layer. For example, U.S. Pat. No. 5,172,197 to Nguyen et al. describes the use of a passivation or stop layer of a lattice-matched, non-oxidizable material forned underlying the source, drain, and gate, and sealingly overlying the donor layer. One drawback of these alternative solutions is that the stop layer tends to increase the gate leakage current, which is undesirable for a good Schottky barrier layer, and adversely affects the electrical performance of the HEMT. A solution, which would prevent degradation of the Schotily barrier layer and/or the donor layer while minimizing any increase in the gate leakage current, has been long sought but has eluded those skilled in the art. As the semiconductor industry is moving to even higher speed applications, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a trrnsistor structure with enhanced electrical performance and improved reliability.
The present invention further provides a transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current.
The present invention still fer provides a transistor structure that includes a substrate, a channel layer formed of a charge transport material over the substrate, a Schottky barrier layer formed of an aluminum-containing material over the channel layer, a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer, and source, drain and gate. The source and the drain are formed in association with the degradation-stop layer. A lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.
The present invention further provides a method for forming a transistor with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5172197 (1992-12-01), Nguyen et al.
H. Rohdin, A. Nagy, V. Robbins, C-Y. Su, A.S. Wakita, J. Seeger, T. Hwang, P. Chye, P.E. Gregory, S.R. Bahl, F.G. Kellert, L.G. Studebaker, D.C. D'Avanzo, and S. Johnsen, “0.1-&mgr;m Gate-Length AllnAs/GaInAs/GaAs MODFET MMIC Process for Applications in High-Speed Wireless Communications”, The Hewlett-Packard Journal, Dec., 1997.
H. Rohdin, A. Nagy, V. Robbins, C-Y. Su, C. Madden, A. Wakita, J. Raggio, and J. Seeger, “Low-Noise, High-Speed Ga47In53As/AI48In52As 0.1 -&mgr;m MODFETs and High-Gain/Bandwidth Three-Stage Amplifier Fabricated on GaAs Substrate”, IEEE 7th International Conference on Indium Phosphide and Related Materials, 1995.
H. Rohdin, C-Y. Su, N. Moll, A. Wakita, A. Nagy, V. Robbins, and M. Kauffman “Semi-Analyticial Analysis for Optimization of 0.1 -&mgr;m InGaAs-Channel MODFETs with Emphasis on On-State Breakdown and Reliability”, IEEE 9th International Conference on Indium Phosphide and Related Materials, 1997.
T. Sonoda, Y. Yamamoto, N. Hayafuji, H. Yoshida, H. Sasaki, T, Kitano, S. Takamiya, and M. Ostubo, “Manufacturability and Reliability if InP HMETs”, Solid-State Electronics, vol. 41, No. 10, pp. 1621-1628, 1997.
K.J. Chen, T. Enoki, K. Maezawa, K. Arai, and M. Yamamoto, “High-Performance Enhancement-Mode InAIAs/InGaAs HEMT's Using Non-Alloyed Ohmic Contact and Pt-Based Buried-Gate”, Proc. InP Rel. Mater., 1996, p. 428-431.
Amano, M, et al., “InAIAs/InGaAs HEMT using UbGaP Schottky Contact Layer”, Seventh International Conference on Indium Phosphide and Related Materials, Japan Society of Applied Physics, May 9-13, 1995, Sapporo, Japan, pp. 416-419.
A.S. Wakita, H. Rohdin, C-Y Su, N. Moll, A. Nagy, and V.M. Robbins, “Drain Resistance Degradation Under High Fields in allnAs/GaInAs MODFETs”, IEEE 9th International Conference on Indium Phosphide and Related Materials, 1997.*
A.S. Wakita, H. Rohdin, V.M. Robbins, N. Moll, C-Y. Su, A. Nagy, and D.P. Basile, “Low-Noise Bias Reliability of AllnAs/GaInAs MODFETs with Linearly Graded Low-Temperature Buffer Layers Grown on GaAs Substrates”, IEEE 10th International Conference on Indium Phosphide and Related Materials, 1998.*
H. Rohdin, A. Wakita, A, Nagy, V. Robbins, N. Moll, and C-Y. Su, “A 0.1 -&mgr;m MHEMT Millimeter-Wave IC Technology Designed for Manufacturability”, Special TWHM-ISA '98 Issue of Solid-State Electronics, Sept., 1998.
Moll Nicolas J.
Rohdin Hans
Su Chung-Yi
Wakita-Oyama Arlene Sachiyo
Agilent Technologie,s Inc.
Anya Igwe U.
Smith Matthew
LandOfFree
Sintered gate schottky barrier fet passivated by a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sintered gate schottky barrier fet passivated by a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sintered gate schottky barrier fet passivated by a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2520074