Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1999-07-22
2000-08-22
Lane, Jack A.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
235492, 34082514, 326 86, G06K 1906, G06F 1318, G08C 1900, G05B 2302
Patent
active
061087513
ABSTRACT:
A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time base whatsoever. The time base in the module can be extremely crude (e.g. more than 4:1 uncertainty). An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. The protocol has been specified so that the module never sources current to the data line, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge from the host. The time base in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge the module does or does not turn on its pull-down transistor, depending on the data value. Thus, the host system, after the falling edge, attempts to pull the data line high again, and then tests the potential of the data line to ascertain the data value.
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Bolan Michael L.
Curry Stephen M.
Deierling Kevin E.
Diaz Donald R.
Kurkowski Hal
Dallas Semiconductor Corporation
Lane Jack A.
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