Single-VCO CDR for TMDS data at gigabit rate

Details Single-VCO CDR for TMDS data at gigabit rate Single-VCO CDR for TMDS data at gigabit rate

2005-05-10

2009-02-17

Pathak, Sudhanshu C (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C375S374000, C375S373000, C331S002000, C331S011000, C327S158000, C713S500000

Reexamination Certificate

active

07492849

ABSTRACT:
A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking signal to a plurality of multiple phased clocking signals. A data capture device acquires the serialized data with each of the plurality of multiple phased clocking signals to create multiple phased data signals. A phase detector determines if the clocking signal is in phase with the recovered serialized data and providing a lead signal and a lag signal indicating whether the clocking signal is in phase with the recovered serialized data. A frequency initializing device assists acquisition of lock of the voltage controlled oscillator to a reference clock signal. A recovered data selector selects which of the multiple phased data signals are to be transferred to external circuitry for further processing.

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