Single transistor E2prom memory device with controlled erasing

Details Single transistor E2prom memory device with controlled erasing Single transistor E2prom memory device with controlled erasing

1997-12-23

2001-12-18

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C365S104000, C365S184000, C365S185030, C365S185180, C365S185220, C365S200000

Reexamination Certificate

active

06331724

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the fabrication and use of semiconductor memory devices. More specifically, a unique single transistor E
2
PROM profile is fabricated using an inventive process flow. Further, a novel memory array is provided which allows flash programming of memory cells sharing a common word line, and selective erasing of individual memory cells, via Fowler-Nordheim tunneling.
BACKGROUND OF THE INVENTION
In the semiconductor industry, non-volatile semiconductor memory is used to store critical programs and data essential for electronic systems, such as computers, telecommunications, industrial and medical instruments, etc. Non-volatile memories are categorized into different types depending upon the relevant technology, including: ROM (read-only memory) which is manufacturer programmed a single time; PROM (programmable read-only memory) which can be programmed by the customer a single time; EPROM (erasable programmable read-only memory) which can be customer programmed, UV-erased, and reprogrammed, generally fewer than one-hundred times, given the cumulative effects of UV exposures on the device arid on device reliability; E
2
PROM (electrically erasable programmable read only memory) which can be programmed and electrically erased by the customer anywhere from 1000-1,000,000 times.
So-called “flash memories” consist of implementations of E
2
PROM for high density manufacturing wherein the memory can be electrically erased in blocks or sectors, rather than at the byte level.
FIG. 1
illustrates a memory array comprising a plurality of memory cells connected along word lines and bit lines. Blocks or sectors of the array may be defined, for example, such as all of the cells along a common source line. The flash memory technology can achieve high densities due to the smaller cell size realized in either a stacked gate or split/step gate cell profile, illustrated in
FIGS. 2A and 2B
, respectively.
FIG. 2A
shows a stacked gate memory cell profile having a floating gate,
11
, and a control gate,
13
, fabricated out of polycrystalline silicon doped with an appropriate doping material to render the polycrystalline silicon conductive (“poly 1” and “poly 2” respectively). The floating gate is electrically separated from the substrate region by an oxide layer of insulating material,
15
. Depending upon the particular device, this intermediate oxide layer is designated as either the gate or tunnel oxide. Those familiar with the art will understand that for the specific purpose of detailing fabrication steps, each use of the term “tunnel oxide” hereinafter is intended to include both the tunnel and the related gate oxide, as appropriate.
FIG. 2A
further illustrates diffused source and drain regions,
17
and
19
, which define a channel in the substrate. The floating gate and the control gate are separated by a layer of insulating material,
12
, typically an interpoly layer of silicon dioxide. In operation, electrons are stored in a capacitive manner at the floating gate. Similarly, the split gate profile of
FIG. 2B
comprises floating polysilicon gate,
14
, and control gate
16
(“poly 1” and “poly 2” respectively) separated by an interpoly dielectric.
The stacked gate profile has the obvious advantage of smaller dimensions, yet is prone to over-erasing whereby the cells readily become depletion-type memory devices when exposed to a negative threshold voltage. On the other hand, the split gate profile is superior in cell reliability, yet requires more surface area than the stacked gate cell. The cell reliability problems of the stacked gate profile are due to cell structure features inherently encountered in stacked gate profiles which have been fabricated in accordance with the current processing standards taught in the art. For example, the typical stacked gate cell structure shown in
FIG. 3
illustrates two cell features, oxide thinning and edge leakage, which have deleterious effects on device reliability. The stacked gate structure of
FIG. 3
is viewed in the word-line direction, perpendicular to the
FIG. 2A
perspective of the same structure viewed in the bit-line direction. Corresponding cell features are denoted with the same reference numerals in
FIG. 3
as were used in FIG.
2
A.
As noted with reference to
FIG. 2A
, the tunnel oxide layer
15
insulates the first polysilicon layer (“poly 1”) from the substrate. Additionally illustrated in
FIG. 3
are the field oxide regions,
18
, which electrically isolate adjacent cells in the array from one another. Under standard processing as taught in the art, the field oxide regions are fabricated first and the tunnel oxide thereafter grown on the substrate between the field oxide regions. Due to the known geometric “bird's beak” effect and the Kooi effect, the so-called “white ribbon” effect, thinning of the layer of tunnel oxide is observed at the junction point between the tunnel oxide layer
15
and the field oxide regions
18
. The thickness reduction due to the geometric effects is generally at least 10% to 15%, while addition of the Kooi effect thickness reduction can result in overall thickness reduction of between 20% and 30%. For advanced MOS devices, such as E
2
PROM or flash E
2
PROM memory devices wherein the gate oxide or tunnel oxide is in the range of ≦120 angstroms, 20%-30% oxide thickness reduction can introduce serious device reliability concerns due to a stronger electric field presence at the junction point between the tunnel oxide layer and the field oxide regions.
Further reliability concerns due to current leakage are observed at the edges of those portions of poly 1 layer
11
which overlap each of the field oxide regions,
18
. Since the poly 1 layer is conformally deposited to create the floating gate structure, a relatively thick layer of poly 1 overlays the field oxide regions. In addition, when the optimal poly 1 layer thickness, in the range of 1000-2500 angstroms, is used, the overlaying portions of the poly 1 layer tend to have sharp edges or corners. These abrupt edges become apparent after the interpoly layer has been formed over the poly 1 layer via a standard, relatively low temperature (below 1050° C.), oxidation step. The sharp edges, or asperities, induce excessive leakage of current between the poly 1 and poly 2 layers, necessarily having a negative impact on device reliability.
It is, therefore, an objective of the present invention to fabricate a high density array of stacked gate memory cells which are not subject to the aforementioned cell reliability concerns.
It is a further objective of the invention to provide a memory array architecture and programming capability whereby individual cells can be erased with the attendant benefit of attaining reliable, programmable, multi-valued logic.
SUMMARY OF THE INVENTION
These and other objectives are realized by the present invention wherein a memory cell having a novel stacked gate cell profile is fabricated in accordance with an inventive process flow.
The device profile has a tunnel oxide formed on a substrate with field oxide regions formed to connect with the tunnel oxide layer edges. No thinning of the edges of the tunnel oxide is observed when the field oxide regions are formed subsequent to the tunnel oxide formation. A first gate, or floating gate, comprises two layers of polysilicon, or analogous material, the first layer deposited over the tunnel oxide between the field oxide regions and the second layer having edges which overlay the field oxide regions. The overlaying floating gate material is thinner than previously achieved in the art and exhibits smooth edges under subsequent processing. Interpoly dielectric material is deposited over the floating gate and the gate profile completed with the fabrication of a control gate over the interpoly dielectric. Source and drain regions are formed in the substrate, in either symmetrical or asymmetrical relationship, beneath the stacked gate.
The unique programming of the inventive structure in a memory array comprises flash pro

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