Single transistor DRAM cell with reduced current leakage and...

Details Single transistor DRAM cell with reduced current leakage and... Single transistor DRAM cell with reduced current leakage and...

2008-05-06

2008-05-06

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S310000, C257S311000, C257S312000, C257S384000, C257S532000

Reexamination Certificate

active

10903084

ABSTRACT:
A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.

REFERENCES:
patent: 6177304 (2001-01-01), Li et al.
patent: 6376298 (2002-04-01), Li et al.
patent: 2002/0027227 (2002-03-01), Kang
patent: 2002/0093030 (2002-07-01), Hsu et al.
patent: 2004/0262660 (2004-12-01), Huang

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