Single transistor charge transfer random access memory

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

active

07973348

ABSTRACT:
A nonvolatile semiconductor memory device is described where each memory cell is composed of a single field effect transistor with a dual gate dielectric comprising a dielectric interfacial layer in contact with a silicon substrate and a ferroelectric layer in between the interfacial layer and the gate electrode. To program (write) the cell the ferroelectric layer is polarized in one of two directions, the ferroelectric polarization creating a large electric field in the interfacial layer. This electric field causes electrons or holes to be transported across the interfacial layer and be trapped in the ferroelectric layer establishing a high (erased) or low (programmed) threshold voltage depending on the direction of the ferroelectric polarization representing the two logic states. To read the memory cell a voltage is applied to the drain of the selected transistor and depending on whether a high or low threshold state was programmed into the cell a low or high current is sensed.

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patent: 6825517 (2004-11-01), Dimmler et al.
patent: 6908772 (2005-06-01), Gnadinger
patent: 2002/0070396 (2002-06-01), Nakajima
patent: 2002/0153542 (2002-10-01), Gnadinger
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patent: 2004/0041186 (2004-03-01), Dimmler et al.
patent: 2004/0211998 (2004-10-01), Araujo et al.
patent: 2006/0017120 (2006-01-01), Sakai
patent: WO2004036651 (2004-04-01), None

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