Single-strobe operation of memory devices

Details Single-strobe operation of memory devices Single-strobe operation of memory devices

2011-02-15

2011-02-15

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S230050, C365S233110

Reexamination Certificate

active

07889578

ABSTRACT:
An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

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