Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1997-12-31
2000-02-01
Garrett, Felisa
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438699, 438700, 438702, 216 18, 216 20, H01L 2100
Patent
active
060202661
ABSTRACT:
A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.
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Hussein Makarem
Lee Kevin J.
Sivakumar Sam
Chin Kin-Chan
Garrett Felisa
Intel Corporation
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