Single stage, level restore circuit with mixed signal inputs

Details Single stage, level restore circuit with mixed signal inputs Single stage, level restore circuit with mixed signal inputs

2005-10-25

2005-10-25

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S098000, C327S208000, C327S211000, C327S212000

Reexamination Certificate

active

06958629

ABSTRACT:
A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.

REFERENCES:
patent: 5278467 (1994-01-01), Nedwek
patent: 6057711 (2000-05-01), Sessions
patent: 6356117 (2002-03-01), Sutherland et al.
patent: 6420907 (2002-07-01), Sutherland et al.
patent: 6590428 (2003-07-01), Barnes

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