Single stage level restore circuit with hold functionality

Details Single stage level restore circuit with hold functionality Single stage level restore circuit with hold functionality

2007-04-10

2007-04-10

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C327S203000, C327S200000

Reexamination Certificate

active

10769172

ABSTRACT:
A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.

REFERENCES:
patent: 5278467 (1994-01-01), Nedwek
patent: 6429692 (2002-08-01), Chan et al.
patent: 6507228 (2003-01-01), Boerstler et al.
patent: 6693476 (2004-02-01), Lin
patent: 6861888 (2005-03-01), Hsieh
patent: 6958629 (2005-10-01), Wijeratne

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