Single stage FIFO memory with a circuit enabling memory to be re

Details Single stage FIFO memory with a circuit enabling memory to be re Single stage FIFO memory with a circuit enabling memory to be re

1997-12-19

2000-04-25

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 53, 710 57, 711100, G06F 1300, G06F 1200

Patent

active

060555882

ABSTRACT:
An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of said first memory means for storing data, and a third memory for storing data connected to the output of said second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

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patent: 4344132 (1982-08-01), Dixon et al.
patent: 4907186 (1990-03-01), Racey
patent: 5309395 (1994-05-01), Dickinson et al.
patent: 5473756 (1995-12-01), Traylor
patent: 5495596 (1996-02-01), Yau

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