Single rail CMOS register array and sense amplifier circuit ther

Static information storage and retrieval – Systems using particular element – Flip-flop

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365190, G11C 1140

Patent

active

047929243

ABSTRACT:
A storage cell and a sense amplifier for use in a register or other memory in an integrated circuit. The storage cell has single-rail input and output, thereby eliminating the necessity of differential input lines and access transistors. The cell also has dual individually-addressable output buses. The sense amplifier includes a master latch connected to the bit line from the storage cell and a slave latch connected to the output. The master latch is normally maintained at its meta-stable condition by a normally-enabled gate. When the content of a storage cell is to be read, the cell outputs a signal onto the bit line, which signal drives the master latch to one side of its meta-stable state. The gate is turned off, allowing the master latch to go to the nearest stable state. The slave latch is connected to the master latch and assumes a state in response thereto. The slave latch and master latch are then disconnected and the master latch returned to its meta-stable state.

REFERENCES:
patent: 3493786 (1970-02-01), Ahrons et al.
patent: 4149268 (1979-04-01), Waters
patent: 4435787 (1984-03-01), Yasuoka
patent: 4441169 (1984-04-01), Sasaki et al.

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