Single-port trace buffer architecture with overflow reduction

Details Single-port trace buffer architecture with overflow reduction Single-port trace buffer architecture with overflow reduction

1998-01-20

2000-11-14

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

150151, 710 40, 710 57, 710244, G06F 1216

Patent

active

061483818

ABSTRACT:
A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.

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