Single-port SRAM with improved read and write margins

Details Single-port SRAM with improved read and write margins Single-port SRAM with improved read and write margins

2008-09-02

2008-09-02

Dinh, Son (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189011, C365S156000, C365S189160

Reexamination Certificate

active

11607509

ABSTRACT:
The present invention relates generally to an integrated circuit (IC) design, and more particularly to a method and apparatus for providing an SRAM cell with improved read and write margins. The method includes providing a first negative voltage to a bit-line and a supply voltage to an inverse bit-line to increase a first potential difference between the bit-line and the inverse bit-line during a write operation of a logic “0.” The method also includes providing the first negative voltage to the inverse bit-line and the supply voltage to the bit-line to increase the first potential difference during a write operation of a data “1.”

REFERENCES:
patent: 7366007 (2008-04-01), Kanehara
patent: 2007/0109878 (2007-05-01), Gouin et al.
patent: 2008/0043544 (2008-02-01), Liaw et al.
Seevinck, Evert et al., ,,Static-Noise Margin Analysis of MOS SRAM Cells, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 748-754.

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