Single port first-in-first-out (FIFO) device having overwrite pr

Details Single port first-in-first-out (FIFO) device having overwrite pr Single port first-in-first-out (FIFO) device having overwrite pr

1996-09-20

1999-10-26

Maung, Zarni

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 57, G06F 1300

Patent

active

059744820

ABSTRACT:
A FIFO single port storage device and methods for using the same are disclosed. The FIFO device includes a single port memory for storing data from a host processor. The single port memory is addressed in a sequential and non-random manner, possibly by a monotonically increasing counter. Control circuitry coupled to the counter and the memory allows for the reading/writing of host data from/to the single port memory. Write protect circuitry prevents host writes to the single port memory by entering a write protect state under combinations of the following conditions: (1) the FIFO is full; (2) the FIFO is nearly full, as defined by a host programmable threshold; (3) the host processor commands the FIFO to enter the write protect state; or (4) the host processor acknowledges a FIFO nearly full interrupt. The errant, or stray, write detection circuitry sets a status flag if a write occurs while the FIFO is in the write protect state. The errant write detection circuity detects stray writes to the memory based on the write protect state value and the quantity of data stored in the FIFO, independent of any particular range of memory protected. Information is read from the FIFO by entering the write protect state, determining the quantity of stored FIFO data, reading the data, and resetting the quantity of data to zero. The FIFO device may be implemented using a field programmable gate array, or FPGA.

REFERENCES:
patent: 3818461 (1974-06-01), Ward et al.
patent: 4258418 (1981-03-01), Heath
patent: 4527233 (1985-07-01), Ambrosius, III et al.
patent: 4873666 (1989-10-01), Lefebvre et al.
patent: 4942553 (1990-07-01), Dalrymple et al.
patent: 5295246 (1994-03-01), Bischoff et al.
patent: 5371877 (1994-12-01), Drako et al.
patent: 5406554 (1995-04-01), Parry
patent: 5557751 (1996-09-01), Banman et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5619687 (1997-04-01), Langan et al.
patent: 5657475 (1997-08-01), Gillespie et al.
patent: 5760792 (1998-06-01), Holt et al.
patent: 5771356 (1998-06-01), Leger et al.
patent: 5784649 (1998-07-01), Begur et al.
patent: 5794037 (1998-08-01), Young
patent: 5797043 (1998-08-01), Lewis et al.
patent: 5832216 (1998-11-01), Szczepanek
patent: 5884099 (1999-03-01), Klingelhofer
patent: 5892979 (1999-04-01), Shiraki et al.
patent: 5901328 (1999-03-01), Ooe
"Fiber-Optic Distributed Data Interface Network Test Adaptor Page Memory Interface Circuit," IBM Tech. Disclosure Bulletin, vol. 34, No. 9, pp. 114-116, Feb. 1992.

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