Single polysilicon level flash EEPROM cell and manufacturing pro

Details Single polysilicon level flash EEPROM cell and manufacturing pro Single polysilicon level flash EEPROM cell and manufacturing pro

1997-06-26

1999-08-10

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257316, 257506, H01L 2972

Patent

active

059362766

ABSTRACT:
A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

REFERENCES:
patent: 4019197 (1977-04-01), Lohstroh et al.

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