Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1993-03-19
1995-05-23
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257322, 257318, 257315, 365185, H01L 27115, H01L 27088, H01L 29788
Patent
active
054183901
ABSTRACT:
An E.sup.2 PROM cell includes a substrate of one conductivity type having source and drain regions of an opposite conductivity type disposed along a surface thereof, with a channel region between the source and drain. An oxide layer is formed over the channel region and includes a relatively thick portion over the channel region, and first and second relatively thin portion over respective portions of the source and drain. Programming of the cell is achieved by electrons passing from the floating gate of the device through the thin oxide portion over the source, while erasing of the cell is undertaken by electrons passing from the drain through the thin oxide portion there over into the floating gate. The cell contains only a single layer of polysilicon, which forms the floating gate.
REFERENCES:
patent: 3952325 (1976-04-01), Beal et al.
patent: 4019197 (1977-04-01), Lohstroh
patent: 4425631 (1984-01-01), Adam
patent: 4924278 (1990-05-01), Logie
patent: 5019879 (1991-05-01), Chin
patent: 5023680 (1991-06-01), Gill et al.
Kume et al., "A 1.28.mu.m.sup.2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM," IEDM 92-991--993 1992.
Jackson Jerome
Lattice Semiconductor Corporation
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