Single polysilicon DRAM cell and array with current gain

Details Single polysilicon DRAM cell and array with current gain Single polysilicon DRAM cell and array with current gain

1999-10-20

2001-07-17

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S344000, C257S408000, C257S322000, C257S390000

Reexamination Certificate

active

06262447

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to DRAM memory cells, and more particularly, to a DRAM memory cell that can be made with a single polysilicon layer and with current gain.
BACKGROUND OF THE INVENTION
The most commonly used DRAM cell structure is the one transistor/one capacitor cell. This DRAM cell structure typically requires the deposition of three layers of conductive polysilicon: one layer for the gate of the transistor, one layer for the bottom storage node of the capacitor, and a third layer for the top storage node of the capacitor. The relatively complex process required to form modern DRAM cells causes practical incompatibility with standard logic processes that typically use only a single polysilicon layer.
Nevertheless, with the trend towards “system-on-a-chip” devices where memory and logic are placed onto a single chip, it is important to develop a DRAM cell structure that will be compatible with logic. There have been prior art attempts to design a DRAM cell structure that can store information without the benefit of a capacitor. An example of such a DRAM cell is disclosed in “A Novel Merged Gain Cell for Logic Compatible High Density DRAMs,” by Mukai et al., Symposium on VLSI Technology Digest of Technical Papers, 1997, at page 155. The DRAM cell disclosed in the Mukai et al. reference shows a single transistor structure that uses n
+
and p
+
regions formed in p-well and n-wells, respectively. Although this proposed DRAM cell design does address some of the problems of embedded DRAM design, the DRAM cell design proposed by the Mukai et al. reference requires very precise manufacturing processes to ensure that the DRAM cell will operate correctly. In addition, the fabrication process is still relatively complicated.
What is needed is a new design for a DRAM cell that can be used in embedded logic applications.
SUMMARY OF THE INVENTION
A two-dimensional array of single polysilicon DRAM cells is disclosed. The array comprises a plurality of DRAM cells arranged in a two-dimensional matrix, wherein each of the DRAM cells comprises: a deep n-well in a silicon substrate; a p-well within said deep n-well; a gate structure over and straddling said deep n-well and said p-well, said gate structure being a stack of a thin gate oxide layer and a conductive layer; and a n
+
region within said p-well and adjacent to a sidewall of said gate structure. The array is connected together by a plurality of column bitlines, each of the column bitlines connected to the n
+
regions of all of the DRAM cells that are in a common column. Further, a plurality of row wordlines are provided, each of the row wordlines connected to the gate structures of all of the DRAM cells that are in a common row.


REFERENCES:
patent: 5998822 (1999-12-01), Wada
patent: 6087690 (2000-07-01), Chi

Affiliated with

Also associated with

Rating

Single polysilicon DRAM cell and array with current gain does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single polysilicon DRAM cell and array with current gain, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single polysilicon DRAM cell and array with current gain will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2488928