Single poly non-volatile memory having a PMOS write path and an

Details Single poly non-volatile memory having a PMOS write path and an Single poly non-volatile memory having a PMOS write path and an

1999-07-14

2000-12-26

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular connection

36518505, 257318, 257321, G11C 1604

Patent

active

061669547

ABSTRACT:
A single-poly, floating gate memory cell includes a PMOS write and an NMOS read path. The memory cell's write path includes a PMOS half-transistor coupled in series with a PMOS write select transistor. The PMOS half-transistor serves as a storage element and includes a P+ drain region, a polysilicon floating gate, and a buried control gate. The read path includes an NMOS read transistor coupled in series with an NMOS read select transistor, where the floating gate of the PMOS half-transistor programming element serves as the gate of the NMOS read transistor. The memory cell is programmed along the PMOS write path by injecting electrons from a P-channel region of the PMOS half-transistor into the floating gate, and is read along the NMOS read path by conducting a channel current through an N-channel region of the NMOS read transistor.

REFERENCES:
patent: 5736764 (1998-04-01), Chang
patent: 5761121 (1998-06-01), Chang
patent: 5761126 (1998-06-01), Chi et al.
patent: 5841165 (1998-11-01), Chang et al.
patent: 6034893 (2000-03-01), Mehta

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