Single-poly neuron MOS transistor

Details Single-poly neuron MOS transistor Single-poly neuron MOS transistor

1996-07-19

1998-05-19

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257316, 257365, 257270, 438264, H01L 29788

Patent

active

057539545

ABSTRACT:
A single-poly neuron transistor is formed by utilizing a series of doped substrate regions in lieu of the input gates that are conventionally used to form neuron transistors. With conventional neuron transistors, the input gates are isolated from the floating gate by a layer of interpoly dielectric. In the present invention, the series of doped substrate regions are isolated from the floating gate by a layer of gate oxide.

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Shibata, T. et al., "Neuron MOS Binary-Logic Integrated Circuits--Part I: Design Fundamentals and Soft-Hardware-Logic Circuit Implementation," IEEE Trans. on Electron Devices, vol. 40, No. 3, pp. 570-575 (Mar. 1993).
Shibata, T. et al., "Neuron MOS Binary-Logic Integrated Circuits--Part II: Simplifying Techniques of Circuit Configuration and their Practical Applications," IEEE Trans. on Electron Devices, vol. 40, No. 5, pp. 974-979 (May 1993).
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