Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-10
2001-08-07
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000
Reexamination Certificate
active
06271560
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a single-poly electrically-programmable read-only-memory (EPROM) cell and, more particularly, to a single-poly EPROM cell with CMOS compatible programming voltages.
2. Description of the Related Art
In the early 1970s, an electrically-programmable read-only-memory (EPROM) cell based on a p-channel MOS transistor with a completely isolated gate was introduced by D. Frohmann-Bentchkowsky (see “A Fully Decoded 2048-bit Electrically Programmable MOS-ROM”, IEEE ISSCC Digest of Technical Papers, p.80, 1971).
FIG. 1
shows a cross-sectional view that illustrates a Frohmann-Bentchkowsky EPROM memory cell
10
. As shown in
FIG. 1
, EPROM cell
10
includes spaced-apart p-type source and drain regions
16
and
18
, respectively, which are formed in an n-type well
14
which, in turn, is formed in a p-type substrate
12
. (Source and drain regions
16
and
18
may alternately be formed in an n-type substrate).
In addition, cell
10
also includes a channel region
20
which is defined between source and drain regions
16
and
18
, and a layer of gate oxide
22
which is formed over channel region
20
. Cell
10
further includes a gate
24
which is formed over gate oxide layer
22
, and a layer of insulation material
26
which, along with gate oxide layer
22
, completely encapsulates gate
24
. Since gate
24
is completely isolated, it is commonly referred to as a floating gate.
In operation, cell
10
is programmed by applying biasing voltages to well
14
and drain
18
which are sufficient to induce avalanche breakdown. For example, avalanche breakdown is induced by applying ground to well
14
and a negative breakdown voltage to drain region
18
(while either grounding or floating source region
16
), or by applying a positive breakdown voltage to well
14
and ground to drain region
18
(while floating or applying the positive breakdown voltage to source region
16
).
The biasing voltages which are sufficient to induce avalanche breakdown establish a strong electric field across the drain-to-well junction depletion region. The strong junction electric field accelerates electrons in the junction depletion region (which are formed from thermally-generated electron-hole pairs) into hot electrons which then have ionizing collisions with the lattice, thereby forming “substrate hot electrons”.
A number of these substrate hot electrons penetrate gate oxide layer
22
and begin accumulating on floating gate
24
due to the relatively positive potential on floating gate
24
with respect to drain region
18
.
The potential on floating gate
24
is defined by the voltages which are coupled to floating gate
24
from well
14
, source region
16
, and drain region
18
, and the surface area of floating gate
24
that is formed over these regions. Thus, since floating gate
24
is only marginally formed over source and drain regions
16
and
18
, the potential on floating gate
24
is primarily determined by the voltage applied to well
14
.
Therefore, when ground is applied to well
14
(and source region
16
), and the negative breakdown voltage is applied to drain region
18
during programming, the potential on floating gate
24
is slightly less than ground which, in turn, is relatively positive with respect to the negative breakdown voltage applied to drain region
18
.
(If a positive breakdown voltage is applied to well
14
and ground is applied to drain region
18
, then floating gate
24
will have a potential slightly less than the positive breakdown voltage which, in turn, is positive with respect to ground which is applied to drain region
18
).
Cell
10
is read by applying ground to well
14
and source region
16
, and a read voltage to drain region
18
. If cell
10
has been programmed, the negative charge on floating gate
24
causes channel region
20
to invert (which inversion is permanent as long as the negative charge remains on floating gate
24
). As a result, the read biasing voltages applied to source and drain regions
16
and
18
cause a current to flow from drain region
18
to source region
16
.
On the other hand, if cell
10
has not been programmed, the slight negative charge which is coupled to floating gate
24
is insufficient to invert channel region
20
. As a result, channel region
20
remains in accumulation. Thus, when the read biasing voltages are applied to source and drain regions
16
and
18
, no current is able to flow.
EPROM cell
10
is erased by irradiating cell
10
with ultraviolet (UV) light to remove the electrons. The UV light increases the energy of the electrons which, in turn, allows the electrons to penetrate the surrounding layers of oxide.
Thus, the Frohmann-Bentchkowsky cell utilizes a p-channel MOS-type device to inject electrons onto the floating gate (as contrasted with more recent EPROM devices that use an n-channel MOS-type device to inject electrons onto the floating gate).
Although some of the first EPROMs sold by Intel™ were based on the Frohmann-Bentchkowsky cell, the cell was soon replaced with alternate cell structures, and has since fallen into relative obscurity.
SUMMARY OF THE INVENTION
The Frohmann-Bentchkowsky memory cell is an electrically-programmable read-only-memory (EPROM) cell that includes spaced-apart source and drain regions which are formed in a substrate material, and a channel region which is defined between the source and drain regions.
In addition, the cell also includes a layer of gate oxide which is formed over the channel region, and a floating gate which is formed over the gate oxide layer. A layer of insulation material, in turn, is formed on the floating gate so that the layer of insulation material and the layer of gate oxide completely encapsulate the floating gate.
Conventionally, the Frohmann-Bentchkowsky EPROM cell is programmed by applying voltages to the drain and substrate which are sufficient to induce avalanche breakdown.
In accordance with the present invention, the Frohmann-Bentchkowsky EPROM cell is programmed by applying a first voltage to the semiconductor material, and a second voltage to the source. In addition, a third voltage is applied to the drain which is sufficient to induce hot punchthrough holes to flow from the source region to the drain region, and insufficient to induce avalanche breakdown at the drain-to-semiconductor material junction.
One of the advantages to using hot punchthrough holes instead of the avalanche effect is that the Frohmann-Bentchkowsky EPROM cell is programmable with CMOS compatible voltages.
A CMOS logic circuit in accordance with the present invention includes a memory cell which is formed in a semiconductor material of a first conductivity type, and a transistor which is formed in a semiconductor material of a second conductivity type.
The memory cell includes spaced-apart source and drain regions of a second conductivity type which are formed in the semiconductor material of the first conductivity type, and a channel region which is defined between the source and drain regions. In addition, the memory cell also includes a layer of gate oxide which is formed over the channel region, and a floating gate which is formed over the layer of gate oxide. The floating gate, in turn, has a physical gate length.
The transistor includes spaced-apart source and drain regions of the first conductivity type which are formed in the semiconductor material of the second conductivity type, and a channel region which is defined between the source and drain regions of the transistor. Further, the transistor also includes a layer of gate oxide which is formed over the channel region of the transistor, and a gate which is formed over the layer of gate oxide of the transistor. In accordance with the present invention, the gate of the transistor has a physical gate length that is greater than the physical gate length of the memory cell.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed d
Bergemont Albert
Kalnitsky Alexander
National Semiconductor Corporation
Pillsbury & Winthrop LLP
Prenty Mark V.
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