Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-01
2003-01-21
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C365S185270, C438S263000, C438S594000
Reexamination Certificate
active
06509606
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a single-poly electrically-programmable read-only-memory (EPROM) cell and, more particularly, to a single-poly EPROM cell that does not incorporate oxide isolation and thereby avoids problems with leakage along the field oxide edge that can lead to degraded data retention.
2. Description of the Related Art
A single-poly electrically-programmable read-only-memory (EPROM) cell is a non-volatile storage device fabricated using process steps that are fully compatible with conventional single-poly CMOS fabrication process steps. As a result, single-poly EPROM cells are often embedded in CMOS logic and mixed-signal circuits.
FIGS. 1A-1C
show a series of views that illustrate a conventional single-poly EPROM cell
100
.
FIG. 1A
shows a top view of cell
100
,
FIG. 1B
shows a cross-sectional view taken along line
1
B-
1
B′ of
FIG. 1A
, while
FIG. 1C
shows a cross-sectional view taken along line
1
C-
1
C′ of FIG.
1
A.
A. Structure of Conventional EPROM Cell
As shown in
FIGS. 1A-1C
, EPROM cell
100
includes spaced-apart source and drain regions
114
and
116
respectively, which are formed in a p-type semiconductor material
112
such as a well or a substrate, and a channel region
118
which is defined between source and drain regions
114
and
116
. Source
114
includes a source contact
115
, and drain
116
includes a drain contact
117
.
As further shown in
FIGS. 1A-1C
, cell
100
also includes an n-well
120
formed over p-type material
112
. Field oxide
105
is formed over p-type material
112
to isolate source region
114
, drain region
116
, and channel region
118
from n-well
120
, and also to isolate EPROM cell
100
from the electrical fields of adjacent devices.
N-well
120
of cell
100
further includes adjoining p+ and n+ contact regions
122
and
124
having n+ contact
123
and p+ contact
125
respectively. Conventional EPROM cell
100
also includes a p-type lightly-doped-drain (PLDD) region
126
which adjoins p+ contact region
122
.
A rectangular control gate region
128
is defined in n-well
120
between PLDD region
126
and field oxide
105
.
A rectangular floating gate oxide
130
is formed over channel region
118
. A rectangular control gate oxide
132
is formed over control gate region
128
. Floating gate oxide
130
and control gate oxide
132
are typically grown at the same time during fabrication of conventional EPROM cell
100
. As a result, oxides
130
and
132
have substantially the same thickness, e.g. approximately 120 Å for 0.5 micron technology, and 70 Å for 0.35 micron technology.
A rectangular floating gate
134
is formed over floating gate oxide
130
, control gate oxide
132
, and a portion of field oxide
105
.
B. Operation of Conventional EPROM Cell
During operation, conventional EPROM cell
100
is programmed by applying a first positive programming voltage of approximately 12 volts to contact regions
122
and
124
, which are shorted together, and a second positive programming voltage of approximately 6-7 volts to drain region
116
. In addition, both p-type material
112
and source region
114
are grounded.
When the positive first programming voltage is applied to contact regions
122
and
124
, a positive potential is induced on floating gate
134
. The positive potential induced on floating gate
134
causes an initial depletion region (not shown) to form in channel region
118
, increasing the potential at the surface of channel region
118
. Source region
114
then injects electrons into the surface of channel region
118
which, in turn, forms a channel of mobile electrons at the inversion layer.
The positive second programming voltage applied to drain region
116
sets up an electric field between source and drain regions
114
and
116
which then accelerates the electrons in the channel. The accelerated electrons then have ionizing collisions that form “hot channel electrons”. The positive potential of floating gate
134
attracts these hot channel electrons, which penetrate gate oxide layer
130
and begin accumulating in floating gate
134
thereby raising the threshold voltage of cell
100
.
Conventional EPROM cell
100
is read by applying a first positive read voltage of approximately 5 volts to contact regions
122
and
124
, and a second positive read voltage of approximately 1-2 volts to drain region
116
. Both p-type material
112
and source region
114
remain grounded.
Under these read bias conditions, a positive potential is induced on floating gate
134
by the above-described mechanism which is (1) sufficient, i.e., larger than the threshold voltage of the cell, to create a channel current that flows from drain region
116
to source region
114
if cell
100
has not been programmed, and (2) insufficient, i.e., less than the threshold voltage of the cell, to create the channel current if cell
100
has been programmed.
The logic state of cell
100
is then determined by comparing the channel current with a reference current.
Conventional EPROM cell
100
is erased by irradiating cell
100
with ultraviolet (UV) light to remove the electrons. The UV light increases the energy of the electrons which, in turn, allows the electrons to penetrate the surrounding layers of oxide.
C. Disadvantages of Conventional EPROM Cell
One problem with the conventional single-poly EPROM cell
100
is that this cell design is prone to leakage of gate oxide over the edge of the field oxide. Specifically, Kooi et al. have discovered that a thin layer of silicon nitride can form in the silicon during oxidation, at the interface with the pad oxide. E. Kooi et al., J. Electrochem, Soc. 123,1117 (1976).
This phenomenon, referred to as the “Kooi effect,” occurs because NH
3
or other nitrogen compounds generated by reaction between H
2
O and the masking nitride during field oxide formation may diffuse through the oxide and react with the silicon substrate. When a gate oxide is subsequently grown in silicon containing this nitride, oxide growth is impeded and the gate oxide is thinned. The resulting highly localized thin gate oxide portions can in turn give rise to problems of low-voltage breakdown of the gate oxide, resulting in leakage. Such gate oxide leakage is particularly problematic in the conventional EPROM cell described above, as the integrity of the voltage stored in the floating gate must remain unaffected over long periods of time.
Therefore, there is a need for a single-poly EPROM cell design that eliminates the field oxide edge as a potential source of leakage.
A second problem of the conventional EPROM cell
100
is the relatively large amount of surface area occupied by the device. As device sizes continue to shrink in response to market demand for greater packing densities, the dimensions of the EPROM cell must also be reduced. Thus, the amount of silicon surface area consumed by EPROM cell
100
looms as an increasingly serious problem.
Much of the surface area occupied by conventional EPROM cell
100
is due to the presence of p+ contact region
122
and PLDD region
126
in n-well
120
. P+ contact region
122
and PLDD region
126
are essential to the operation of conventional EPROM cell
100
because of a prior unmasked threshold voltage adjustment implant (V
Tp
) into the surface of n-well
120
. The relationship between P+ contact region
122
, PLDD region
126
, and the V
Tp
implant is now described in detail.
As discussed above, a conventional EPROM cell is programmed by applying a positive voltage to both n+ contact region
124
and p+ contact region
122
. The positive voltage applied to n+ contact region
124
in conjunction with the potential of floating gate
134
draws electrons away from the surface of the n-well adjacent to control gate oxide
132
.
Under the voltages typically used to program the conventional EPROM cell, the surface of n-well
120
is normally not rich enough in electrons to maintain ac
Bergemont Albert
Chi Min-hwa
Merrill Richard B.
National Semiconductor Corporation
Stallman & Pollock LLP
Weiss Howard
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