Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-01-25
2004-01-13
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185140
Reexamination Certificate
active
06678190
ABSTRACT:
The present invention relates to a semiconductor device, and more specifically, to a single poly embedded one-time programming (OTP) memory.
BACKGROUND OF THE INVENTION
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the size reduction of a device. Thanks to their advantages, such as non-volatility, fast access time and low power dissipation, non-volatile memory can be applied as portable handy equipments, solid-state camera and PC cards. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), and EEPROM (electrically erasable programmable read only memory). Different types of devices have been developed for specific applications. These parts have been developed with a focus on the high endurance and high-speed requirements. EEPROM needs multi-layer of polysilicon and silicon dioxide, therefore, multi-masking are used during the fabrication, thereby increasing the time for manufacturing the devices. One of the present researches is focus on how to integrate the manufacture process to reduce the cost. One of the approaches is to integrate the memory process with the CMOS fabrication. Up to now, many approaches toward to the formation of the EPROM and EEPROM by using one single poly process. In the technique, the control gate is buried in silicon bulk by ion implantation. EPROM or OTP, which is compatible with the single poly process, plays more important role in the semiconductor field.
A prior art that relates to the field is disclosed in the U.S. Pat. No. 6,174,759 to Verhaar, entitled “Method of manufacturing a semiconductor device”. The assignee is U.S. Philips Corporation (New York, N.Y.) and filed the prior art on May 3, 1999. The method disclosed a process that can integrate with the CMOS process. Lucent Technologies, Inc. disclosed a single poly EEPROM on May 31, 2000 in U.S. Pat. No. 6,191,980. The device includes control device, switch device and erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell can be safely erased without risking the junction breakdowns. Mosel Vitelic, Inc. (Hsinchu, TW) disclosed a single poly memory and filed on Jun. 17, 1998, entitled “Single-poly flash memory cell for embedded application and related methods”. The prior art can be found in U.S. Pat. No. 6,044,018. The prior art includes a single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate is electrically connected to a PMOS floating gate.
In the article IEEE transaction on electron device, Vol. 37, No. 3, March 1990 p. 675, in which disclosed single poly-Si EEPROM. The structure includes an embedded control gate that is formed by ion implantation. The cell includes separated transistor and coupled capacitor and can be manufacturable by standard CMOS process. The further technique that can be compatible with the CMOS can be found in IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 29, No. 3, 1994, p. 311. The structure includes NMOS and PMOS, the inversion layer under the PMOS gate and p+ doped region act as the control gate. When positive voltage applies to the p+ doped region, the voltage level of the floating gate determines the capacitance ratio of the NMOS and PMOS. The art may be formed by standard CMOS process. The structure refers to SIPPOS (single poly pure CMOS).
FIG. 1
shows the layout of prior single poly non-volatile memory, the structure includes n+ doped region under the floating gate and buried in the substrate. The structure occupies too much area.
FIG. 2
shows another type of layer according to the prior art. The structure is consisted of a capacitor and a PMOS. The technique has to provide space for forming the capacitor.
SUMMARY OF THE INVENTION
The object of the present invention is to disclose nonvolatile memory or one-time programming (OTP) memory. One of the features includes that the device consists of two serial connected P-type metal-oxide-semiconductor transistors.
An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors. Wherein a first P-type metal-oxide semiconductor transistor acts as a select transistor, a second P-type metal-oxide semiconductor transistor, wherein a gate of the second P-type metal-oxide semiconductor transistor serves as a floating gate, biasing a drain of the second P-type metal-oxide semiconductor transistor to a first negative bias, thereby providing a second negative bias on the floating gate to perform programming mode without applying a certain bias on a control gate.
An erasable programmable read only memory without a control gate comprises a doped region formed by ion implantation in a substrate. A first conductive area is covered on the substrate and forms a first cross structure with a first overlap area to act as a select transistor gate and is connected to a select gate voltage (V
SG
) A second conductive region located at side of the first conductive region and on the substrate and forms a second cross structure with a second overlap area to act as a floating gate. Wherein a feature of the erasable programmable read only memory is that a control gate is omitted, thereby reducing device size and the process is compatible with CMOS process.
REFERENCES:
patent: 5940324 (1999-08-01), Chi et al.
patent: 5959885 (1999-09-01), Rao
patent: 6044018 (2000-03-01), Sung et al.
patent: 6166954 (2000-12-01), Chern
patent: 6174759 (2001-01-01), Verhaar et al.
patent: 6191980 (2001-02-01), Kelley et al.
patent: 6324097 (2001-11-01), Chen et al.
patent: 6512700 (2003-01-01), McPartland et al.
An EPROM Cell Structure for ErLD's Compatible with Single Poly-Si Gate Process, IEZZ Transactions on Electron Devices, vol. 37, No. 3, Mar. 1990, p. 675-p. 679.
A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes, IEEE Journal of Solid-State Circuits, vol. 29, No. 3. Mar. 1994, p. 311-316.
Hsu Ching-Hsiang
Shen Shih-Jye
Yang Ching-Sung
e-Memory Technology, Inc.
Hsu Winston
Phung Anh
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