Single-poly EEPROM on a negatively biased substrate

Details Single-poly EEPROM on a negatively biased substrate Single-poly EEPROM on a negatively biased substrate

2003-01-22

2004-11-09

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000, C257S322000, C257S401000, C438S176000, C438S197000, C438S594000

Reexamination Certificate

active

06815757

ABSTRACT:

TECHNICAL FIELD
The invention relates to electronic semiconductor devices, and more particularly, to devices and methods for forming an EEPROM cell on a negatively biased substrate. The invention may be practiced using standard semiconductor processing techniques.
BACKGROUND OF THE INVENTION
A popular form of nonvolatile memory known in the arts is the single polysilicon EEPROM (Electrically Erasable Programmable Read Only Memory). EEPROMs are a convenient and versatile form of nonvolatile memory that, under appropriate operating conditions, can be programmed, erased, and reprogrammed thousands of times.
In general, a single polysilicon EEPROM structure includes four distinct elements defined here for the discussion below: the floating gate, the control gate, the tunneling region, and the read transistor. The floating gate, as the term is used herein, is defined as the entire length of polysilicon which extends over the read transistor, or sense FET read channel, the control gate, and the tunneling region. The floating gate extends into two diffusions in scaled proportions forming a ratio of a larger capacitor to a smaller capacitor. The control gate is defined by the diffusion forming the lower plate of the larger capacitor with respect to the floating gate in the capacitor ratio. The tunneling region is defined by the diffusion forming the lower plate of the smaller capacitor with respect to the floating gate in the capacitor ratio. The floating gate crosses over a third diffusion region where it forms the gate of the read transistor. The terminals of the EEPROM device are the control gate, the tunneling region, and the read transistor source, drain, and backgate nodes. The floating gate is not considered a terminal in the discussion below because it can not be directly accessed as a floating node.
A single polysilicon EEPROM typically uses a variant of a MOSFET with two gates, a diffused control gate and a polysilicon floating gate not electrically connected to any other part of the circuit. Before the EEPROM memory cell is programmed, no charge exists on the floating gate and the read transistor operates as an enhancement mode transistor. To program the device, a large voltage is applied to the control gate while all other terminals are grounded. The large voltage of the control gate creates an electric field in the insulating oxide between the floating gate and the read transistor channel and between the floating gate and tunneling region. This field attracts electrons from the substrate. Thus, a negative charge accumulates on the floating gate.
The negative charge that accumulates on the floating gate reduces the strength of the electric field in the oxide until it is incapable of contributing more electrons to the floating gate. The charge becomes trapped on the floating gate and the device is said to be in a “programmed state”. Once programmed, the charge trapped on the floating gate causes electrons to be repelled from the surface of the substrate. Thus the threshold voltage of the device is raised significantly above that of the device in an unprogrammed state. Once programmed, the floating gate retains its trapped charge even when the power supply is off. Extrapolated experimental data indicates that an EEPROM device may remain in the programmed state for many years.
To erase the device, a large voltage is applied to the tunneling region while all other terminals are grounded. The large voltage of the tunneling region creates an electric field in the insulating oxide between floating gate and tunneling region. This field attracts electrons from the floating gate. Thus, a positive charge (absence of electrons) accumulates on the floating gate.
The positive charge that accumulates on the floating gate reduces the strength of the electric field in the oxide until it is incapable of removing more electrons from the floating gate. Positive charge becomes trapped on the floating gate and the device is said to be in a “erased state”. Once erased, the charge trapped on the floating gate causes electrons to be attaracted to the surface of the substrate. Thus the threshold voltage of the device is reduced significantly below that of the device in an unprogrammed state. Once erased, the floating gate retains its trapped charge even when the power supply is off. Extrapolated experimental data indicates that an EEPROM device may remain in the erased state for many years.
Reading the EEPROM device is accomplished by applying a gate-to-source voltage above the threshold voltage for an erased device and below the threshold voltage for a programmed device. At the drain terminal of the read transistor, an erased device conducts electricity, and a programmed device does not, allowing the stored data value to be determined. An EEPROM device can be electrically erased and subsequently reprogrammed.
Characteristically EEPROM devices used in the arts have employed a grounded substrate and a grounded SNwell diffusion capacitor plate and are capable of storing programmed data for years. In applications having a negative potential difference between the SNwell capacitor plates and the substrate however, significant problems are encountered. In an EEPROM cell on a negatively biased substrate, the probability of electron injection from the substrate into the oxide is greatly increased. The injected electrons form an electric field which counteracts the positive charge stored on the floating gate of an erased cell, thus causing data loss in a matter of hours or days. Attempts to address this problem have included using polysilicon fuses for long-term nonvolatile data storage. This approach however has serious limitations in terms of reliability due to variations in individual fuses and their “blowing” characteristics, including the possibility that a polysilicon fuse may regrow over time. Another attempted solution known in the arts is to use level-shifting of data into and out of standard EEPROM cells so that data is stored away from negatively biased substrate conditions. Major disadvantages of this approach include increased circuit complexity and the greater area required for the additional level-shifting circuits. It would be useful and advantageous in the arts to provide an EEPROM device capable of reliably storing data in applications having a negative bias on the substrate.
SUMMARY OF THE INVENTION
In general, the invention provides an EEPROM cell for use on a negatively biased substrate and associated methods of manufacturing. The EEPROM is isolated from the underlying substrate by an interposing DNwell.
According to one aspect of the invention, a method of making a floating gate transistor for use as an EEPROM cell includes steps of forming a DNwell in a P-type substrate and forming an isolated EEPROM cell on the DNwell.
According to another aspect of the invention, a method of making an EEPROM cell for use on a negatively biased substrate includes a step of forming a buried N-type layer (NBL), followed by a step of depositing a P-type epitaxial layer. Further steps include the formation of a DNwell in the P-type substrate. The DNwell includes a void in the center over the NBL pattern such that the DNwell forms an enclosure fully contacting the perimeter of the NBL, providing an isolated P-type region. The DNwell also underlies the tunneling region, floating gate region, and control region and is electrically coupled to a fixed DC voltage or ground. Further steps include the formation of a first SNwell in the DNwell to create a tunneling region and a first capacitor. A second SNwell is formed in the DNwell of the control region with a second capacitor and control gate. A sense transistor is formed on the isolated P-type region. Steps for forming oxide layers over the cell are followed by the formation of a polysilicon floating gate on the oxide layers. Standard CMOS processing steps follow to complete the EEPROM cell.
According to still another aspect of the invention, a representative embodiment of a floating gate transistor for use as an EEPROM cell incorporates a P-type substrate

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