Single phase pseudo-static instruction translation look-aside bu

Details Single phase pseudo-static instruction translation look-aside bu Single phase pseudo-static instruction translation look-aside bu

1995-09-06

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711156, 711128, G06T 1100

Patent

active

058025944

ABSTRACT:
An instruction translation look-aside buffer (iTLB) for attaining very high data processing throughput comprises a 2.sup.n -way set associative data array having m sets, where m and n are both integers greater than or equal to one, with associated data and tag arrays. A set address selects one of the m sets for reading, resulting in a readout of all 2.sup.n ways of the tag, valid and data arrays. Comparison logic determines if a match exists between the 2.sup.n tags read out from the tag array with a portion of the linear address. A "hit" to a certain way causes a hit line signal to select data for the corresponding way, which is output from a 2.sup.n :1 static multiplexer and contains the physical address translation. Each of the hit lines are precharged during a first phase of a clock cycle. The comparison logic operating during a second phase of a clock cycle. Thus, the matching is accomplished in a single clock cycle.

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Hennessy et al., "Computer Organization and Design: The Hardware/Software Interface", Morgan Kauffman Publishers, pp. 283, 509, B-19, B-30 and B-31, 1994.
Handy, Jim, "The Cache Memory Book", Academic Press, Inc., pp. 22, 44, and 45, 1993.
Short, Kenneth L., "Microprocessors and Programmed Logic", Prentice-Hall, p. 69, section 3.2.2, 1987.

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