Single phase edge trigger register

Details Single phase edge trigger register Single phase edge trigger register

2000-05-12

2002-05-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S112000, C326S115000

Reexamination Certificate

active

06388471

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits and, more specifically, to logic circuits designed for high-speed operation, such as domino logic circuits.
2. Description of the Related Art
Performance goals of processors increase with every generation, and progressively more sophisticated architectures are required to implement their complex functions. Advanced architectures require long pipelines operating at very high frequencies. These higher frequencies demand increased usage of sophisticated circuit design styles like domino circuits.
Domino circuits, also known as dynamic circuit, increase the speed performance of logic circuits by reducing the capacitance associated with the use of P-type metal oxide semiconductors (“MOS”). Domino circuits accomplish this by precharging a series of logic gates during a first dock phase, or precharge cycle, and evaluating the intended logic function during the next clock phase, or evaluation cycle.
However, a problem with a typical domino circuit is that if the input data changes its value during the evaluation cycle after the node values are set, the voltage potential at the precharged node may float until the next precharge cycle. A node value is voltage potential at the node and is typically being set at the beginning of the evaluation cycle. The float or float node indicates the voltage potential at a node or node value is not being driven. Accordingly, a float may cause an unknown logic value at the node. Thus, the domino circuit may give a wrong value when a float node is being accessed during the evaluation cycle.
SUMMARY OF THE INVENTION
A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in the storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state in the storage device according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.
Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.


REFERENCES:
patent: 5148061 (1992-09-01), Hsueh et al.
patent: 6014041 (2000-01-01), Somaskhar et al.
patent: 6046608 (2000-04-01), Theogarajan

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