Single NMOS device memory cell and array

Details Single NMOS device memory cell and array Single NMOS device memory cell and array

2007-05-22

2007-05-22

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S177000

Reexamination Certificate

active

10957986

ABSTRACT:
The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the “on” state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.

REFERENCES:
patent: 5109361 (1992-04-01), Yim et al.
patent: 5208780 (1993-05-01), Iwase et al.
patent: 5365487 (1994-11-01), Patel et al.

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