Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-26
2001-01-30
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S738000, C438S622000
Reexamination Certificate
active
06180512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of ultra large scale (ULSI) integrated chips (IC) in general, and in particular, to the fabrication of metal lines and vias in a semiconductor substrate by using a single phase-shifting mask applied to dual damascene process.
2. Description of the Related Art
Masks in general are tools that are used to delineate the size and shape of features that form the integrated circuits in a semiconductor chip . Ultimately, the level of integration of chips, whether they are ULSI or VLSI (very large scale integrated) is determined by how small and how precisely the images of those features can be formed on a mask and then transferred onto the semiconductor substrate from which the chips are fabricated. As the number of features, such as devices, metal lines and interconnections have been increasing dramatically, along with the number of semiconductor layers to accommodate the increasing number of components, the issue of the number of masks as well as the number of mask processes that are needed has gained importance in the semiconductor industry. This invention discloses a method for combining two masks into one in a dual damascene process where the advantages of the single mask are realized as explained below.
In related art, Damascene process, or inlaid metal patterning in pre-formed grooves, is usually a preferred method of fabricating interconnections for an integrated circuit. Unlike with Damascene interconnections which will be described more in detail later, the more conventional interconnections are formed by blanket depositing a conductive material on an insulation layer such as silicon oxide, and then etching the desired wiring pattern on the layer. The vertical connections between the wiring layers are made separately by forming holes in the insulation layers separating the metallized layers and then filling them with the same or a different conductive material. It will be appreciated that as the number of wiring layers increase, the number of masks required will also increase proportionately.
Normally, a semiconductor chip contains one or more metal wiring layers that are separated from each other by an insulating layer and are further separated by still another insulating layer from the devices that are formed near the surface of the semiconductor that forms the base of the chip. The wiring stripes are connected to each other and to the devices at the appropriate places by means of holes that are filled with metal through the insulating layers. The holes that connect the metal lines to each other through the insulating layer are called via holes, while the holes that reach the underlying devices through its insulating layer are called contact holes. Typically, the holes are etched into an insulating layer after the latter has been deposited on the semiconductor substrate on which the chips are fabricated. It is common practice to next blanket deposit metal on the insulating layer thereby filling the holes and then forming the metal lines by etching through a patterned photo resist formed on the metal layer. For the first metal layer, electrical contact is made with the underlying devices through contact holes, or windows, that allow the metal to descend through the dielectric insulator to the devices. For the second and subsequent wiring layers, the process is repeated and the contact between the metal layers is made through via holes that allow the metal to descend to the lower metal layer(s). It is also common practice to fill the holes separately with metal to form metal plugs first, planarize or smoothen them next with respect to the surface of the insulating layer and then deposit metal layer to make contact with the via plugs and then subtractively etch as before to form the required “personalized” wiring layer.
To provide robust contact area at the junction where the metal lines contact the devices or the via plugs in the case of multilayer wiring, it is usually necessary to increase the dimensions of the various features in he metal line and the holes to compensate for overlay errors and process bias inherent in lithographic process. This increase in the size of the design ground rules results in a significant loss in circuit layout density. Furthermore, there is considerable development effort expended on photolithographic equipment and processes to make improvement in overlay error and process tolerances. To minimize the chip area devoted to overlay tolerance and lithography costs, several “self-aligned” processes have been developed by workers in the field.
There are also other problems associated with forming contacts between metal layers in a substrate. Where contact windows are etched into a dielectric layer, the sides of the contact windows must be sloped to guarantee good continuity of the metal layer as it descends into the contact window. The steeper the slope, the more likely it is the metallurgy will have breaks at the edges of the contact windows. However, the use of a gradually sloped sidewall to guarantee metal line continuity takes up valuable chip area and prevents contact windows from being packed as closely as desired. In addition, the use of contact windows creates an irregular and nonplanar surface which makes it difficult to fabricate the subsequent interconnecting layers as shown in FIG.
1
.
The structure shown in
FIG. 1
is a typical example of a semiconductor substrate fabricated using prior art techniques. After having defined device regions represented by reference (
11
) on substrate (
10
), a first insulating layer (
12
) is formed and patterned thereon. First level metal layer (
13
) is next deposited to make contact with region (
11
) through contact window (
14
). Similarly, the second level metal layer (
16
) makes contact with metal layer (
13
) through via hole (
17
) patterned in second insulating layer (
15
). The structure is passivated with a third insulating layer (
18
). Although the structure depicted in
FIG. 1
is not to scale, it exemplifies a very irregular surface which creates reliability problems. One such problem is the potential short at location (S) between the first and second levels of metal layers, due to the thinning of the insulating layer therebetween, and still another one is the risk of a potential open circuit at locations (O), due to the thinning of the metal layer at that location.
One solution that is found in prior art in addressing the problems cited above is the dual damascene process. In its simplest form, this process starts with an insulating layer which is first formed on a substrate and then planarized. Then horizontal trenches and vertical holes are etched into the insulating layer corresponding to the required metal line pattern and hole locations, respectively, that will descend down through the insulating layer to the underlying features, that is, to device regions if through the first insulating layer, or to the next metal layer down if through an upper insulating layer in the substrate structure. Metal is next deposited over the substrate thereby filling the trenches and the holes, and hence forming metal lines and the interconnect holes simultaneously. As a final step, the resulting surface is planarized using the well-known chemical-mechanical polish (CMP), and readied to accept another dual damascene structure, that is, integrally inlaid wiring both in the horizontal trenches and vertical holes, hence the duality of the process.
A dual damascene structure before and after CMP is shown in
FIG. 2
a
and
FIG. 2
b.
Two photolithographic processes and two insulator layers separated by an etch stop layer are employed to achieve the shown structure as follows: a starting planarized surface (
30
) is provided with patterned first level metal (
31
). A first layer of insulator (
32
) is deposited over a fist level of patterned metal to which contacts are to be selectively established. The first layer is planarized and then covered by an etch stop material (
33
). Contact holes are defined
Ackerman Stephen B.
Bowers Charles
Hawranek Scott J.
Industrial Technology Research Institute
Saile George O.
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