Boots – shoes – and leggings
Patent
1994-06-14
1995-03-14
Harvey, Jack B.
Boots, shoes, and leggings
365 51, 365 63, 326 39, 326 41, G06F 738
Patent
active
053981987
ABSTRACT:
An arithmetic and logic unit implemented in a memory array. The memory array has a plurality of memory cells each with a memory storage element and each accessible via a word line and at least one bit line, The arithmetic and logic unit comprises a plurality of logic circuits coupled to the word and bit lines in place of the memory storage elements of certain memory cells, Each of a plurality of pull down logic circuits implements an arithmetic and/or logic function,
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Mahant-Shetti Shivaling S.
Swamy Shobana
Donaldson Richard
Harvey Jack B.
Hiller William E.
Lane Jack A.
Rutkowski Peter
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