Single-instruction multiple-data processor with input and output

Details Single-instruction multiple-data processor with input and output Single-instruction multiple-data processor with input and output

1997-12-18

2000-04-04

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

712 20, 712 22, 711217, 711218, G06F 1576

Patent

active

060473665

ABSTRACT:
A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

REFERENCES:
patent: 5253308 (1993-10-01), Johnson
patent: 5321510 (1994-06-01), Childers et al.
patent: 5555428 (1996-09-01), Radigan et al.
patent: 5752068 (1998-05-01), Gilbert
patent: 5765015 (1998-06-01), Wilkinson et al.

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