Single-instruction-multiple-data processing using multiple banks

Details Single-instruction-multiple-data processing using multiple banks Single-instruction-multiple-data processing using multiple banks

1996-08-19

1998-11-17

Lall, Parshotam S.

395563, 39580004, G06F 930

Patent

active

058389849

ABSTRACT:
A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.

REFERENCES:
patent: 4791555 (1988-12-01), Garcia
patent: 5115393 (1992-05-01), Kashiyama et al.
patent: 5678058 (1997-10-01), Sato

Affiliated with

Also associated with

Rating

Single-instruction-multiple-data processing using multiple banks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single-instruction-multiple-data processing using multiple banks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single-instruction-multiple-data processing using multiple banks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-895876