Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer
Reexamination Certificate
1994-11-21
2001-10-09
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Frame buffer
C345S574000
Reexamination Certificate
active
06300963
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to image display systems, and more particularly to systems that process digital image data and use a spatial light modulator to display real-time images.
BACKGROUND OF THE INVENTION
Real-time display systems based on spatial light modulators (SLMs) are increasingly being used as an alternative to display systems using cathode ray tubes (CRTs). SIM systems provide high resolution displays without the bulk and power consumption of a CRT system.
Digital micromirror devices (DMDs) are a type of SLM, and may be used in projection display applications. A DMD has an array of micro-mechanical pixel elements, each having a mirror and a memory cell. Each pixel element is individually addressable by electronic data. Depending on the state of its addressing signal, each mirror element is tilted so that it either does or does not reflect light to the image plane. Other SIMs operate on similar principles, with pixel elements that emit or reflect light simultaneously with other pixel elements, such that a complete image frame is generated by addressing pixel elements rather than by scanning them.
For processing data in an SIM-based systems, as is the case with other digital image processing systems, the processor operates on pixel data. Interlaced data is arranged pixel-by-pixel, row-by-row, and field-by-field. Scan conversion techniques are used to generate frames from fields. In a standard television system, for example, images are transmitted at 30 frames per second, and each frame lasts for approximately 33.3 milliseconds. Non-interlaced data is already arranged as frames.
Processing tasks such as colorspace conversion and scaling, as well as scan conversion, are performed on the pixel data.
However, in an SLM-based system, the SLM must receive the data in “bit-planes”. In other words, pixel data must be reformatted into bit-level data so that each pixel element can be “on” or “off” a length of time corresponding to the value of its pixel data. Various modulation schemes determine how long each pixel is on or off, and permit greyscale and color images to be displayed. A bit-plane represents all bits of all pixels having the same digital weight. For pixels having an n-bit resolution, there are n bit-planes per display frame.
SLM-based systems use a “display memory” to provide bit-planes of data to the SLM. Existing display memories are “double buffered”, so that they can store data for a current frame while data for a next frame is being written in. This permits each frame of data to be read out of memory and displayed on the SIM during its own frame period. Many display memories operating in this double-buffered mode require a capacity of two frames of data. A variation of double-buffering is dynamically allocating memory space so as to reduce the required capacity. U.S. Pat. Ser. No. 07/755.883, entitled “Dynamic Memory Allocation For Frame Buffer for Spatial Light Modulator”, assigned to Texas Instruments Incorporated, discusses these methods of using a display memory.
SUMMARY OF THE INVENTION
A first aspect of the invention is a display memory for use in a digital display system having a processor for performing image processing and having a spatial light modulator (SIM) with bit-addressable pixel elements for generating an image. A first frame of samples of pixel data is written to the memory during a first frame period. This first frame is stored in the memory such that it may be read out in bit-planes comprised of one bit per sample. A second frame comprised of samples of pixel data is written to the memory during a second frame period, such that each sample of the second frame is written over the corresponding sample of the first frame. This second frame is also stored so that it may be read out in bit-planes comprised of one bit per sample. During either the first frame period or the second frame period, a bit-plane of data is read from the memory, with this reading step being performed with data from the first frame and data from the second frame. The reading step is repeated such that at least the same number of bit-planes as the number of bits representing each pixel are read out during a display period. Each of the bit-planes is delivered to the spatial light modulator for display.
A technical advantage of the invention is that less memory capacity is required than for double-buffered memories. This reduces the cost of the system.
REFERENCES:
patent: 4789854 (1988-12-01), Ishii
patent: 4818932 (1989-04-01), Odenheimer
patent: 4847809 (1989-07-01), Suzuki
patent: 4868556 (1989-09-01), Murakami et al.
patent: 4910670 (1990-03-01), Smith et al.
patent: 5179372 (1993-01-01), West et al.
patent: 5254984 (1993-10-01), Wakeland
patent: 5255100 (1993-10-01), Urbanus
patent: 5307056 (1994-04-01), Urbanus
patent: 5339116 (1994-08-01), Urbanus et al.
patent: 5371519 (1994-12-01), Fisher
patent: 5438376 (1995-08-01), Watanabe
patent: 0 530 760 A2 (1993-03-01), None
patent: 1262586 (1989-10-01), None
patent: 4326393 (1992-11-01), None
Doherty Donald B.
Urbanus Paul M.
Brady III Wade James
Brill Charles A.
Mengistu Amare
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Single-frame display memory for spatial light modulator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single-frame display memory for spatial light modulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single-frame display memory for spatial light modulator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2556512