Single event upset resilient programmable interconnect

Details Single event upset resilient programmable interconnect Single event upset resilient programmable interconnect

2010-03-01

2010-12-14

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Reliability

Parasitic prevention in integrated circuit structure

C326S038000

Reexamination Certificate

active

07852108

ABSTRACT:
In one embodiment of the present invention, a programmable interconnect circuit is provided. The programmable interconnect circuit includes first and second static random access memory cells, each having a first output and a second output. The second output is an inversion of the first output. First and second pass gates are each coupled to one of the first and second outputs of the respective first and second memory cells. First and second lock-state circuits are coupled to the respective first and second memory cells. In response to a configuration status signal and the first output of one of the memory cells being asserted to a low voltage, the respective lock-state circuit is configured to maintain the one of the outputs of the respective memory cell at the low voltage.

REFERENCES:
patent: 2007/0242537 (2007-10-01), Golke et al.
patent: 2008/0074145 (2008-03-01), Sidhu et al.
patent: 2009/0034312 (2009-02-01), Lawrence et al.
U.S. Appl. No. 12/354,202, filed Jan. 15, 2009, de Jong.

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