Single event upset mitigation

Details Single event upset mitigation Single event upset mitigation

2011-08-02

2011-08-02

Ismail, Shawki S (Department: 2819)

Electronic digital logic circuitry

Reliability

Redundant

C326S014000

Reexamination Certificate

active

07990173

ABSTRACT:
A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.

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Lima, Fernanda et al., “Designing Fault Tolerant Systems into SRAM-based FPGAs,”Proc. of the 40thDesign Automation Conference(DAC'03), Jun. 2, 2003, pp. 650-655, ACM, New York, New York, USA.

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