Single event upset in SRAM cells in FPGAs with high...

Details Single event upset in SRAM cells in FPGAs with high... Single event upset in SRAM cells in FPGAs with high...

2006-01-03

2006-01-03

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S363000

Reexamination Certificate

active

06982451

ABSTRACT:
SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

REFERENCES:
patent: 6049487 (2000-04-01), Plants et al.
patent: 6369630 (2002-04-01), Rockett
patent: 6656803 (2003-12-01), Chan
patent: 6717233 (2004-04-01), Haddad et al.

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