Single event upset immune logic family

Details Single event upset immune logic family Single event upset immune logic family

2002-12-16

2004-06-22

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Reliability

Redundant

C326S009000, C326S112000, C326S119000

Reexamination Certificate

active

06753694

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to single event upset (SEU) prevention in high density electronic circuits. More particularly, the present invention presents a family of SEU immune logic circuits.
BACKGROUND
Single event upset (SEU) is a phenomenon that sometimes occurs to high density electronics when subjected to radiation fields. When critical dimensions of integrated circuits drop below a certain threshold, Alpha particles and other energetic species impinging on the active integrated circuit or device can cause false bits, lock-up, or catastrophic failure. SEU is a change of state or transient induced by an energetic particle such as a cosmic ray or proton in a device. SEU may occur in digital, analog, and optical components or may have effects in surrounding interface circuitry. This is considered a significant problem in designing electronics for reliable operation in space.
Previous SEU immunity for logic families such as those illustrated in U.S. Pat. No. 5,418,473 have relied on internal feedback and signaling which does not drive from rail-to-rail of the power supplies and is not able to provide strong, symmetrical output drive signals. This results in slow logic operation. The present invention overcomes the aforementioned shortcomings without having to rely on internal feedback designs.
SEU immunity has mainly been emphasized for memory elements. The present invention, however, expands SEU immunity to all logic functions such that upsets can neither propagate through a logic network, nor corrupt memory storage.
SUMMARY
The present invention is comprised of a family of logic gates that provide single event upset (SEU) immunity. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected (i.e., tri-state), which preserves the previous output value. Since, SEU events only affect one of the logic elements in the pair, an upset can not propagate through other logic elements because of the tri-state function.
A single event upset (SEU) immune logic function circuit according to the present invention is comprised of a plurality of logic sub-circuits wherein each logic sub-circuit is comprised of redundant inputs. A chosen implementation circuit functions such that when the redundant inputs are not the same the output becomes tri-state and the output from the previous stage is unchanged. Otherwise, when the redundant inputs are the same the output is driven in accordance with the desired logic function.


REFERENCES:
patent: 5311070 (1994-05-01), Dooley
patent: 5418473 (1995-05-01), Canaris
patent: 6198334 (2001-03-01), Tomobe et al.
patent: 6278287 (2001-08-01), Baze
patent: 6377097 (2002-04-01), Shuler, Jr.

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