Single event upset immune keeper circuit and method for dual...

Details Single event upset immune keeper circuit and method for dual... Single event upset immune keeper circuit and method for dual...

2006-07-11

2006-07-11

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000

Reexamination Certificate

active

07075337

ABSTRACT:
A method includes precharging a first dynamic node, precharging a second dynamic node, and maintaining a first logic state of a signal on the first dynamic node responsive to a second logic state of a signal on the second dynamic node. The method further includes maintaining the second logic state of the signal on the second dynamic node responsive to the first logic state of the signal on the first dynamic node.

REFERENCES:
patent: 5382844 (1995-01-01), Knauer
patent: 6046606 (2000-04-01), Chu et al.
patent: 6282140 (2001-08-01), Phan et al.
patent: 6696874 (2004-02-01), Wood

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