Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
2000-07-19
2002-06-18
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257S618000
Reexamination Certificate
active
06407444
ABSTRACT:
This invention relates to semiconductor devices, and more particularly, to the protection of such devices against single event upset damage caused by high-energy impacts on the devices.
BACKGROUND OF THE INVENTION
A semiconductor device may be susceptible to damage from various types of radiation and particles that impinge on the device. In one type of damage, electron-hole pairs are created when energetic particles, such as cosmic rays, alpha particles, and/or protons, are incident upon on the semiconductor device. The electrons or the holes may migrate as a current to the active device structure (e.g., a transistor) of the semiconductor device. This damage-induced current may be misinterpreted by the active device structure and cause it to perform improperly. The malfunction, termed a Single Event Upset (SEU), may lead to disruption of the electronic circuitry.
SEU damage is a particularly significant problem for semiconductor devices used in space applications. High-energy damage sources are plentiful. Protection by using thick, impenetrable cases is not possible due to their high weight. Alternative approaches are to provide for redundancy of the circuitry and to use complex error detection and correction techniques. The former increases the size of the semiconductor device and increases its power consumption. The latter adds cost and increases the computing time.
The present inventor is particularly concerned with high-speed heterojunction bipolar semiconductor device structures for use in space applications. One form of this technology is based on the use of indium phosphide-based semiconductor substrates. There is no known approach for hardening such devices against SEU damage.
Accordingly, there is a need for an improved approach to the prevention of SEU damage in semiconductor devices, particularly those of the indium phosphide type. This approach must be compatible with the operation of the semiconductor devices, and must not significantly increase the size and/or power consumption of the devices. The present invention fulfills this need, and further provides related advantages.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device having an active device structure, such as a transistor, with additional structure that reduces the susceptibility of the active device structure to damage from Single Event Upset (SEU). The features that impart the increased damage tolerance are buried within the substrate of the semiconductor device, except for an external electrical contact. They therefore occupy very little surface area of the semiconductor device, so that it remains compact. Substantially no additional power is consumed in achieving the protection of the active device structure.
In accordance with the invention, a semiconductor device comprises a substrate, an active device structure, such as a transistor having a collector, disposed adjacent to a top surface of the substrate, and a biasing structure. The biasing structure includes a buried electrode disposed below the top surface of the substrate, and an electrical contact at a surface of the substrate and in electrical communication with the buried electrode. The semiconductor device desirably further includes a biasing source having a voltage output which applies a biasing voltage to the electrical contact of greater than about 0.2 volts and typically greater than about 0.7 volts. The biasing voltage applied to the electrical contact is normally in the range of from about 0.2 volts to about 5 volts, most preferably from about 0.7 volts to about 5 volts.
The active device structure preferably includes a transistor having a collector. The buried electrode is preferably disposed below the top surface of the substrate by a distance of from about 0.1 micrometers to about 2 micrometers.
The substrate is preferably made of a material having a trap density which increases with increasing distance from a top surface of the substrate. That is, the electrical resistivity of the substrate decreases with increasing distance from the top surface. The substrate is therefore semi-insulating near the top surface, and semi-conducting at greater depths below the top surface. The preferred substrate material comprises indium phosphide (InP).
In one embodiment, the buried electrode extends perpendicular to the top surface of the substrate. In another embodiment, the buried electrode includes a first portion that extends perpendicular to the top surface of the substrate and a second portion, in electrical communication with the first portion, that extends parallel to the top surface of the substrate and at a distance of from about 0.1 to about 2 micrometers below the top surface of the substrate. Other operable structures for the buried electrode may also be used.
When high energy radiation or particles impact and penetrate the substrate, electrons and holes are produced. For example, when an energetic particle penetrates the substrate, a narrow column of charge is produced corresponding to the track of the column. In the absence of the present biasing structure, at least some of the charge deposited into the substrate migrates to the active device structure. The load capacitance of the active device structure is charged, inducing a voltage at the base of the load transistor. If sufficient voltage is established, the next transistor turns on, leading to a Single Event Upset (SEU) of the circuit.
The biased buried electrode of the present invention collects the migrating charge, preventing it from reaching the active device structure. The node voltage of the active device structure is prevented from dropping below the voltage (usually around 0.7 volts for an InP-based transistor) that will turn on the next-stage circuit, thereby preventing the SEU of the circuit. The actual value of the biasing voltage depends on the general semiconductor type and architecture, the nature of the active device structure, and its positioning within the circuit.
The present approach is implemented by depositing the metallic biasing structure in conjunction with the formation of the substrate of the semiconductor device. Little surface area of the semiconductor device is taken up by the biasing structure, so that the total area of the semiconductor device is not substantially enlarged. A single biasing structure may serve several active device structures having the same biasing requirement. The operation of the individual active device structures is not affected by the subsurface biasing voltage applied in the present SEU hardening approach, as the biasing voltage is localized and well below the active device structures.
Other features and advantages of the present invention will be apparent from the following more detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. The scope of the invention is not, however, limited to this preferred embodiment.
REFERENCES:
patent: 5436195 (1995-07-01), Kimura et al.
patent: 6034415 (2000-03-01), Johnson et al.
patent: 6218895 (2001-04-01), De et al.
patent: 62221157 (1987-09-01), None
Dickey Thomas L
Gudmestad Terje
Hughes Electronics Corp.
Rafter John R.
Tran Minh Loan
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