Single event upset hardening circuits, devices and methods

Details Single event upset hardening circuits, devices and methods Single event upset hardening circuits, devices and methods

1990-02-05

1992-12-29

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

307441, 307443, 307451, 257921, H01L 2702, H03K 19003, H03K 190948

Patent

active

051756056

ABSTRACT:
The present invention provides a unique circuit and layout methods for improving upon series redundant circuits. A substitution device, comprising a pair of series connected N or P FETs for respective single FETs, can be further hardened or enhanced against cosmic rays, particles, etc. by spacing the P FETs a predetermined distance apart so that an ion or other particle cannot strike or affect both channels simultaneously, thus avoiding upset. When these devices are placed in cells (i.e., ASIC) in logic or the like circuits, the predetermined spacing is related to cell height. Also, alignment of the gates of the substitution device on a common axis minimizes the window of a satellite through which a particle could effectively strike the common gate axis possibly to upset both gates.

REFERENCES:
patent: 4833347 (1989-05-01), Rabe
patent: 4937473 (1990-06-01), Statz et al.

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